Overview
Request 5558 (accepted)
- Update to new version 8.050.00
- Port patches r8168-kernel_version.patch and r8168-configuration.patch
- Created by bitstreamout almost 3 years ago
- In state accepted
-
Package maintainer:
bitstreamout
r8168.changes
Changed
x
1
2
-------------------------------------------------------------------
3
-Tue Aug 24 13:01:21 UTC 2021 - Luigi Baldoni <aloisio@gmx.com>
4
+Tue May 10 10:30:35 UTC 2022 - Werner Fink <werner@suse.de>
5
6
-- Update to version 8.049.02
7
+- Update to new version 8.050.00
8
+- Port patches r8168-kernel_version.patch and r8168-configuration.patch
9
10
-------------------------------------------------------------------
11
Thu Jan 21 15:49:06 UTC 2021 - Werner Fink <werner@suse.de>
12
r8168.spec
Changed
19
1
2
#
3
# spec file for package r8168
4
#
5
-# Copyright (c) 2021 Packman Team <packman@links2linux.de>
6
+# Copyright (c) 2019 Packman Team <packman@links2linux.de>
7
# Copyright (c) 2017 SUSE LINUX Products GmbH, Nuernberg, Germany.
8
#
9
# All modifications and additions to the file contributed by third parties
10
11
12
#!BuildIgnore: enough-build-resources
13
Name: r8168
14
-Version: 8.049.02
15
+Version: 8.050.00
16
Release: 0
17
Summary: Device driver for RealTek Gigabit Ethernet controllers
18
License: GPL-2.0-or-later
19
r8168-configuration.patch
Changed
12
1
2
1 file changed, 1 insertion(+)
3
4
--- src/Makefile
5
-+++ src/Makefile 2018-01-10 14:35:59.981468278 +0000
6
-@@ -44,6 +44,7 @@ ENABLE_S0_MAGIC_PACKET = n
7
++++ src/Makefile 2022-05-10 10:26:59.851240712 +0000
8
+@@ -48,6 +48,7 @@ CONFIG_CTAP_SHORT_OFF = n
9
ifneq ($(KERNELRELEASE),)
10
obj-m := r8168.o
11
r8168-objs := r8168_n.o r8168_asf.o rtl_eeprom.o rtltool.o
12
r8168-kernel_version.patch
Changed
50
1
2
2 files changed, 18 insertions(+), 1 deletion(-)
3
4
--- src/r8168.h
5
-+++ src/r8168.h 2021-01-25 09:25:12.615124741 +0000
6
-@@ -116,6 +116,10 @@ do { \
7
++++ src/r8168.h 2022-05-10 10:26:28.831787721 +0000
8
+@@ -121,6 +121,10 @@ do { \
9
} while (0)
10
#endif //LINUX_VERSION_CODE < KERNEL_VERSION(2,6,15)
11
12
13
#if defined(skb_vlan_tag_present) && !defined(vlan_tx_tag_present)
14
#define vlan_tx_tag_present skb_vlan_tag_present
15
--- src/r8168_n.c
16
-+++ src/r8168_n.c 2021-01-25 11:42:13.268115241 +0000
17
-@@ -60,11 +60,16 @@
18
++++ src/r8168_n.c 2022-05-10 10:26:28.871787016 +0000
19
+@@ -61,11 +61,16 @@
20
#include <linux/rtnetlink.h>
21
#include <linux/completion.h>
22
23
24
#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,37)
25
#include <linux/prefetch.h>
26
#endif
27
-@@ -459,8 +464,12 @@ static void rtl8168_set_rx_mode(struct n
28
+@@ -571,8 +576,12 @@ static void rtl8168_set_rx_mode(struct n
29
#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,6,0)
30
static void rtl8168_tx_timeout(struct net_device *dev, unsigned int txqueue);
31
#else
32
33
static struct net_device_stats *rtl8168_get_stats(struct net_device *dev);
34
static int rtl8168_rx_interrupt(struct net_device *, struct rtl8168_private *, napi_budget);
35
static int rtl8168_change_mtu(struct net_device *dev, int new_mtu);
36
-@@ -27948,8 +27957,12 @@ static void
37
+@@ -28748,8 +28757,12 @@ static void
38
rtl8168_tx_timeout(struct net_device *dev, unsigned int txqueue)
39
#else
40
static void
41
42
{
43
struct rtl8168_private *tp = netdev_priv(dev);
44
unsigned long flags;
45
-@@ -28655,7 +28668,7 @@ process_pkt:
46
+@@ -29435,7 +29448,7 @@ process_pkt:
47
48
if (rtl8168_rx_vlan_skb(tp, desc, skb) < 0)
49
rtl8168_rx_skb(tp, skb);
50
r8168-8.049.02.tar.gz/Makefile -> r8168-8.050.00.tar.gz/Makefile
Changed
10
1
2
# r8168 is the Linux device driver released for Realtek Gigabit Ethernet
3
# controllers with PCI-Express interface.
4
#
5
-# Copyright(c) 2021 Realtek Semiconductor Corp. All rights reserved.
6
+# Copyright(c) 2022 Realtek Semiconductor Corp. All rights reserved.
7
#
8
# This program is free software; you can redistribute it and/or modify it
9
# under the terms of the GNU General Public License as published by the Free
10
r8168-8.049.02.tar.gz/src/Makefile -> r8168-8.050.00.tar.gz/src/Makefile
Changed
28
1
2
# r8168 is the Linux device driver released for Realtek Gigabit Ethernet
3
# controllers with PCI-Express interface.
4
#
5
-# Copyright(c) 2021 Realtek Semiconductor Corp. All rights reserved.
6
+# Copyright(c) 2022 Realtek Semiconductor Corp. All rights reserved.
7
#
8
# This program is free software; you can redistribute it and/or modify it
9
# under the terms of the GNU General Public License as published by the Free
10
11
ENABLE_S0_MAGIC_PACKET = n
12
CONFIG_DYNAMIC_ASPM = y
13
ENABLE_USE_FIRMWARE_FILE = n
14
+CONFIG_CTAP_SHORT_OFF = n
15
16
ifneq ($(KERNELRELEASE),)
17
obj-m := r8168.o
18
19
r8168-objs += r8168_firmware.o
20
EXTRA_CFLAGS += -DENABLE_USE_FIRMWARE_FILE
21
endif
22
+ ifeq ($(CONFIG_CTAP_SHORT_OFF), y)
23
+ EXTRA_CFLAGS += -DCONFIG_CTAP_SHORT_OFF
24
+ endif
25
else
26
BASEDIR := /lib/modules/$(shell uname -r)
27
KERNELDIR ?= $(BASEDIR)/build
28
r8168-8.049.02.tar.gz/src/Makefile_linux24x -> r8168-8.050.00.tar.gz/src/Makefile_linux24x
Changed
10
1
2
# r8168 is the Linux device driver released for Realtek Gigabit Ethernet
3
# controllers with PCI-Express interface.
4
#
5
-# Copyright(c) 2021 Realtek Semiconductor Corp. All rights reserved.
6
+# Copyright(c) 2022 Realtek Semiconductor Corp. All rights reserved.
7
#
8
# This program is free software; you can redistribute it and/or modify it
9
# under the terms of the GNU General Public License as published by the Free
10
r8168-8.049.02.tar.gz/src/r8168.h -> r8168-8.050.00.tar.gz/src/r8168.h
Changed
123
1
2
# r8168 is the Linux device driver released for Realtek Gigabit Ethernet
3
# controllers with PCI-Express interface.
4
#
5
-# Copyright(c) 2021 Realtek Semiconductor Corp. All rights reserved.
6
+# Copyright(c) 2022 Realtek Semiconductor Corp. All rights reserved.
7
#
8
# This program is free software; you can redistribute it and/or modify it
9
# under the terms of the GNU General Public License as published by the Free
10
11
#endif
12
#endif
13
14
+#if LINUX_VERSION_CODE < KERNEL_VERSION(3,6,0)
15
+#define eth_random_addr(addr) random_ether_addr(addr)
16
+#endif //LINUX_VERSION_CODE < KERNEL_VERSION(3,6,0)
17
+
18
#if LINUX_VERSION_CODE < KERNEL_VERSION(3,3,0)
19
#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,0,0)
20
#define netdev_features_t u32
21
22
#define DASH_SUFFIX ""
23
#endif
24
25
-#define RTL8168_VERSION "8.049.02" NAPI_SUFFIX FIBER_SUFFIX REALWOW_SUFFIX DASH_SUFFIX
26
+#define RTL8168_VERSION "8.050.00" NAPI_SUFFIX FIBER_SUFFIX REALWOW_SUFFIX DASH_SUFFIX
27
#define MODULENAME "r8168"
28
#define PFX MODULENAME ": "
29
30
#define GPL_CLAIM "\
31
-r8168 Copyright (C) 2021 Realtek NIC software team <nicfae@realtek.com> \n \
32
+r8168 Copyright (C) 2022 Realtek NIC software team <nicfae@realtek.com> \n \
33
This program comes with ABSOLUTELY NO WARRANTY; for details, please see <http://www.gnu.org/licenses/>. \n \
34
This is free software, and you are welcome to redistribute it under certain conditions; see <http://www.gnu.org/licenses/>. \n"
35
36
37
#define RTL8168_LINK_TIMEOUT (1 * HZ)
38
#define RTL8168_ESD_TIMEOUT (2 * HZ)
39
40
-#define NUM_TX_DESC 1024 /* Number of Tx descriptor registers */
41
-#define NUM_RX_DESC 1024 /* Number of Rx descriptor registers */
42
+#define MAX_NUM_TX_DESC 1024 /* Maximum number of Tx descriptor registers */
43
+#define MAX_NUM_RX_DESC 1024 /* Maximum number of Rx descriptor registers */
44
+
45
+#define MIN_NUM_TX_DESC 32 /* Minimum number of Tx descriptor registers */
46
+#define MIN_NUM_RX_DESC 32 /* Minimum number of Rx descriptor registers */
47
+
48
+#define NUM_TX_DESC 256 /* Number of Tx descriptor registers */
49
+#define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
50
51
#define RX_BUF_SIZE 0x05F3 /* 0x05F3 = 1522bye + 1 */
52
-#define R8168_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
53
-#define R8168_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
54
55
#define OCP_STD_PHY_BASE 0xa400
56
57
58
u32 pci_sn_h;
59
};
60
61
+/* Flow Control Settings */
62
+enum rtl8168_fc_mode {
63
+ rtl8168_fc_none = 0,
64
+ rtl8168_fc_rx_pause,
65
+ rtl8168_fc_tx_pause,
66
+ rtl8168_fc_full,
67
+ rtl8168_fc_default
68
+};
69
+
70
struct rtl8168_private {
71
void __iomem *mmio_addr; /* memory map physical address */
72
struct pci_dev *pci_dev; /* Index of PCI device */
73
74
u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
75
u32 dirty_rx;
76
u32 dirty_tx;
77
+ u32 num_rx_desc; /* Number of Rx descriptor registers */
78
+ u32 num_tx_desc; /* Number of Tx descriptor registers */
79
struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
80
struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
81
dma_addr_t TxPhyAddr;
82
dma_addr_t RxPhyAddr;
83
- struct sk_buff *Rx_skbuffNUM_RX_DESC; /* Rx data buffers */
84
- struct ring_info tx_skbNUM_TX_DESC; /* Tx data buffers */
85
+ struct sk_buff *Rx_skbuffMAX_NUM_RX_DESC; /* Rx data buffers */
86
+ struct ring_info tx_skbMAX_NUM_TX_DESC; /* Tx data buffers */
87
unsigned rx_buf_sz;
88
struct timer_list esd_timer;
89
struct timer_list link_timer;
90
91
u8 duplex;
92
u32 speed;
93
u32 advertising;
94
+ enum rtl8168_fc_mode fcpause;
95
u16 eeprom_len;
96
u16 cur_page;
97
u32 bios_setting;
98
99
u8 HwSuppEsdVer;
100
u8 TestPhyOcpReg;
101
u16 BackupPhyFuseDout_15_0;
102
+ u16 BackupPhyFuseDout_31_16;
103
u16 BackupPhyFuseDout_47_32;
104
u16 BackupPhyFuseDout_63_48;
105
106
107
CFG_METHOD_31,
108
CFG_METHOD_32,
109
CFG_METHOD_33,
110
+ CFG_METHOD_34,
111
+ CFG_METHOD_35,
112
CFG_METHOD_MAX,
113
CFG_METHOD_DEFAULT = 0xFF
114
};
115
116
#define NIC_RAMCODE_VERSION_CFG_METHOD_28 (0x0019)
117
#define NIC_RAMCODE_VERSION_CFG_METHOD_29 (0x0055)
118
#define NIC_RAMCODE_VERSION_CFG_METHOD_31 (0x0003)
119
+#define NIC_RAMCODE_VERSION_CFG_METHOD_35 (0x0004)
120
121
//hwoptimize
122
#define HW_PATCH_SOC_LAN (BIT_0)
123
r8168-8.049.02.tar.gz/src/r8168_asf.c -> r8168-8.050.00.tar.gz/src/r8168_asf.c
Changed
10
1
2
# r8168 is the Linux device driver released for Realtek Gigabit Ethernet
3
# controllers with PCI-Express interface.
4
#
5
-# Copyright(c) 2021 Realtek Semiconductor Corp. All rights reserved.
6
+# Copyright(c) 2022 Realtek Semiconductor Corp. All rights reserved.
7
#
8
# This program is free software; you can redistribute it and/or modify it
9
# under the terms of the GNU General Public License as published by the Free
10
r8168-8.049.02.tar.gz/src/r8168_asf.h -> r8168-8.050.00.tar.gz/src/r8168_asf.h
Changed
10
1
2
# r8168 is the Linux device driver released for Realtek Gigabit Ethernet
3
# controllers with PCI-Express interface.
4
#
5
-# Copyright(c) 2021 Realtek Semiconductor Corp. All rights reserved.
6
+# Copyright(c) 2022 Realtek Semiconductor Corp. All rights reserved.
7
#
8
# This program is free software; you can redistribute it and/or modify it
9
# under the terms of the GNU General Public License as published by the Free
10
r8168-8.049.02.tar.gz/src/r8168_dash.h -> r8168-8.050.00.tar.gz/src/r8168_dash.h
Changed
10
1
2
# r8168 is the Linux device driver released for Realtek Gigabit Ethernet
3
# controllers with PCI-Express interface.
4
#
5
-# Copyright(c) 2021 Realtek Semiconductor Corp. All rights reserved.
6
+# Copyright(c) 2022 Realtek Semiconductor Corp. All rights reserved.
7
#
8
# This program is free software; you can redistribute it and/or modify it
9
# under the terms of the GNU General Public License as published by the Free
10
r8168-8.049.02.tar.gz/src/r8168_fiber.h -> r8168-8.050.00.tar.gz/src/r8168_fiber.h
Changed
49
1
2
# r8168 is the Linux device driver released for Realtek Gigabit Ethernet
3
# controllers with PCI-Express interface.
4
#
5
-# Copyright(c) 2021 Realtek Semiconductor Corp. All rights reserved.
6
+# Copyright(c) 2022 Realtek Semiconductor Corp. All rights reserved.
7
#
8
# This program is free software; you can redistribute it and/or modify it
9
# under the terms of the GNU General Public License as published by the Free
10
11
12
enum {
13
FIBER_STAT_NOT_CHECKED = 0,
14
- FIBER_STAT_CONNECT,
15
+ FIBER_STAT_CONNECT_EEPROM,
16
FIBER_STAT_DISCONNECT,
17
+ FIBER_STAT_CONNECT_GPO,
18
FIBER_STAT_MAX
19
};
20
21
#define HW_FIBER_MODE_ENABLED(_M) ((_M)->HwFiberModeVer > 0)
22
+#define HW_FIBER_STATUS_CONNECTED(_M) (((_M)->HwFiberStat == FIBER_STAT_CONNECT_EEPROM) || ((_M)->HwFiberStat == FIBER_STAT_CONNECT_GPO))
23
+#define HW_FIBER_STATUS_DISCONNECTED(_M) ((_M)->HwFiberStat == FIBER_STAT_DISCONNECT)
24
25
+struct rtl8168_private;
26
27
-
28
-void rtl8168_hw_init_fiber_nic(struct net_device *dev);
29
-void rtl8168_hw_fiber_nic_d3_para(struct net_device *dev);
30
-void rtl8168_hw_fiber_phy_config(struct net_device *dev);
31
-void rtl8168_hw_switch_mdi_to_fiber(struct net_device *dev);
32
-void rtl8168_hw_switch_mdi_to_nic(struct net_device *dev);
33
-unsigned int rtl8168_hw_fiber_link_ok(struct net_device *dev);
34
-void rtl8168_check_fiber_link_status(struct net_device *dev);
35
-void rtl8168_check_hw_fiber_mode_support(struct net_device *dev);
36
-void rtl8168_set_fiber_mode_software_variable(struct net_device *dev);
37
-
38
+void rtl8168_hw_init_fiber_nic(struct rtl8168_private *tp);
39
+void rtl8168_hw_fiber_nic_d3_para(struct rtl8168_private *tp);
40
+void rtl8168_hw_fiber_phy_config(struct rtl8168_private *tp);
41
+void rtl8168_hw_switch_mdi_to_fiber(struct rtl8168_private *tp);
42
+void rtl8168_hw_switch_mdi_to_nic(struct rtl8168_private *tp);
43
+unsigned int rtl8168_hw_fiber_link_ok(struct rtl8168_private *tp);
44
+void rtl8168_check_fiber_link_status(struct rtl8168_private *tp);
45
+void rtl8168_check_hw_fiber_mode_support(struct rtl8168_private *tp);
46
+void rtl8168_set_fiber_mode_software_variable(struct rtl8168_private *tp);
47
48
#endif /* _LINUX_R8168_FIBER_H */
49
r8168-8.049.02.tar.gz/src/r8168_firmware.c -> r8168-8.050.00.tar.gz/src/r8168_firmware.c
Changed
10
1
2
# r8168 is the Linux device driver released for Realtek Gigabit Ethernet
3
# controllers with PCI-Express interface.
4
#
5
-# Copyright(c) 2021 Realtek Semiconductor Corp. All rights reserved.
6
+# Copyright(c) 2022 Realtek Semiconductor Corp. All rights reserved.
7
#
8
# This program is free software; you can redistribute it and/or modify it
9
# under the terms of the GNU General Public License as published by the Free
10
r8168-8.049.02.tar.gz/src/r8168_firmware.h -> r8168-8.050.00.tar.gz/src/r8168_firmware.h
Changed
10
1
2
# r8168 is the Linux device driver released for Realtek 2.5Gigabit Ethernet
3
# controllers with PCI-Express interface.
4
#
5
-# Copyright(c) 2021 Realtek Semiconductor Corp. All rights reserved.
6
+# Copyright(c) 2022 Realtek Semiconductor Corp. All rights reserved.
7
#
8
# This program is free software; you can redistribute it and/or modify it
9
# under the terms of the GNU General Public License as published by the Free
10
r8168-8.049.02.tar.gz/src/r8168_n.c -> r8168-8.050.00.tar.gz/src/r8168_n.c
Changed
3346
1
2
# r8168 is the Linux device driver released for Realtek Gigabit Ethernet
3
# controllers with PCI-Express interface.
4
#
5
-# Copyright(c) 2021 Realtek Semiconductor Corp. All rights reserved.
6
+# Copyright(c) 2022 Realtek Semiconductor Corp. All rights reserved.
7
#
8
# This program is free software; you can redistribute it and/or modify it
9
# under the terms of the GNU General Public License as published by the Free
10
11
#define FIRMWARE_8168EP_3 "rtl_nic/rtl8168ep-3.fw"
12
#define FIRMWARE_8168H_1 "rtl_nic/rtl8168h-1.fw"
13
#define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw"
14
+#define FIRMWARE_8168H_3 "rtl_nic/rtl8168h-3.fw"
15
#define FIRMWARE_8168FP_3 "rtl_nic/rtl8168fp-3.fw"
16
#define FIRMWARE_8168FP_4 "rtl_nic/rtl8168fp-4.fw"
17
18
19
CFG_METHOD_31 = {"RTL8168FP/8111FP", },
20
CFG_METHOD_32 = {"RTL8168FP/8111FP", FIRMWARE_8168FP_3},
21
CFG_METHOD_33 = {"RTL8168FP/8111FP", FIRMWARE_8168FP_4},
22
+ CFG_METHOD_34 = {"RTL8168FP/8111FP", FIRMWARE_8168FP_4},
23
+ CFG_METHOD_35 = {"RTL8168H/8111H", FIRMWARE_8168H_3},
24
CFG_METHOD_DEFAULT = {"Unknown", },
25
};
26
27
28
0xff7e5880,
29
Jumbo_Frame_9k),
30
31
+ _R("RTL8168FP/8111FP",
32
+ CFG_METHOD_34,
33
+ RxCfg_128_int_en | RxEarly_off_V2 | Rx_Single_fetch_V2 | (RX_DMA_BURST << RxCfgDMAShift),
34
+ 0xff7e5880,
35
+ Jumbo_Frame_9k),
36
+
37
+ _R("RTL8168H/8111H",
38
+ CFG_METHOD_35,
39
+ RxCfg_128_int_en | RxEarly_off_V2 | Rx_Single_fetch_V2 | (RX_DMA_BURST << RxCfgDMAShift),
40
+ 0xff7e5880,
41
+ Jumbo_Frame_9k),
42
+
43
_R("Unknown",
44
CFG_METHOD_DEFAULT,
45
(RX_DMA_BURST << RxCfgDMAShift),
46
47
MODULE_FIRMWARE(FIRMWARE_8168EP_3);
48
MODULE_FIRMWARE(FIRMWARE_8168H_1);
49
MODULE_FIRMWARE(FIRMWARE_8168H_2);
50
+MODULE_FIRMWARE(FIRMWARE_8168H_3);
51
MODULE_FIRMWARE(FIRMWARE_8168FP_3);
52
MODULE_FIRMWARE(FIRMWARE_8168FP_4);
53
#endif
54
55
static void rtl8168_down(struct net_device *dev);
56
57
static int rtl8168_set_mac_address(struct net_device *dev, void *p);
58
-void rtl8168_rar_set(struct rtl8168_private *tp, uint8_t *addr);
59
+void rtl8168_rar_set(struct rtl8168_private *tp, const u8 *addr);
60
static void rtl8168_desc_addr_fill(struct rtl8168_private *);
61
static void rtl8168_tx_desc_init(struct rtl8168_private *tp);
62
static void rtl8168_rx_desc_init(struct rtl8168_private *tp);
63
64
seq_printf(m, "chipset\t%d\n", tp->chipset);
65
seq_printf(m, "chipset_name\t%s\n", rtl_chip_infotp->chipset.name);
66
seq_printf(m, "mtu\t%d\n", dev->mtu);
67
- seq_printf(m, "NUM_RX_DESC\t0x%x\n", NUM_RX_DESC);
68
+ seq_printf(m, "NUM_RX_DESC\t0x%x\n", tp->num_rx_desc);
69
seq_printf(m, "cur_rx\t0x%x\n", tp->cur_rx);
70
seq_printf(m, "dirty_rx\t0x%x\n", tp->dirty_rx);
71
- seq_printf(m, "NUM_TX_DESC\t0x%x\n", NUM_TX_DESC);
72
+ seq_printf(m, "NUM_TX_DESC\t0x%x\n", tp->num_tx_desc);
73
seq_printf(m, "cur_tx\t0x%x\n", tp->cur_tx);
74
seq_printf(m, "dirty_tx\t0x%x\n", tp->dirty_tx);
75
seq_printf(m, "rx_buf_sz\t0x%x\n", tp->rx_buf_sz);
76
77
tp->chipset,
78
rtl_chip_infotp->chipset.name,
79
dev->mtu,
80
- NUM_RX_DESC,
81
+ tp->num_rx_desc,
82
tp->cur_rx,
83
tp->dirty_rx,
84
- NUM_TX_DESC,
85
+ tp->num_tx_desc,
86
tp->cur_tx,
87
tp->dirty_tx,
88
tp->rx_buf_sz,
89
90
static int rtl8168_proc_open(struct inode *inode, struct file *file)
91
{
92
struct net_device *dev = proc_get_parent_data(inode);
93
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,17,0)
94
+ int (*show)(struct seq_file *, void *) = pde_data(inode);
95
+#else
96
int (*show)(struct seq_file *, void *) = PDE_DATA(inode);
97
+#endif //LINUX_VERSION_CODE >= KERNEL_VERSION(5,17,0)
98
99
return single_open(file, show, dev);
100
}
101
102
rtl8168_mac_ocp_write(tp, addr, RegValue);
103
}
104
105
-/*
106
static void
107
rtl8168_clear_mcu_ocp_bit(
108
struct rtl8168_private *tp,
109
110
0
111
);
112
}
113
-*/
114
115
static void
116
rtl8168_set_mcu_ocp_bit(
117
118
case CFG_METHOD_31:
119
case CFG_METHOD_32:
120
case CFG_METHOD_33:
121
+ case CFG_METHOD_34:
122
default:
123
ocp_reg_mutex_oob = 0x110;
124
ocp_reg_mutex_ib = 0x114;
125
126
case CFG_METHOD_31:
127
case CFG_METHOD_32:
128
case CFG_METHOD_33:
129
+ case CFG_METHOD_34:
130
default:
131
ocp_reg_mutex_oob = 0x110;
132
ocp_reg_mutex_ib = 0x114;
133
134
if (tp->mcfg != CFG_METHOD_20 && tp->mcfg != CFG_METHOD_23 &&
135
tp->mcfg != CFG_METHOD_26 && tp->mcfg != CFG_METHOD_27 &&
136
tp->mcfg != CFG_METHOD_28 && tp->mcfg != CFG_METHOD_31 &&
137
- tp->mcfg != CFG_METHOD_32 && tp->mcfg != CFG_METHOD_33) {
138
+ tp->mcfg != CFG_METHOD_32 && tp->mcfg != CFG_METHOD_33 &&
139
+ tp->mcfg != CFG_METHOD_34) {
140
multi_fun_sel_bit = 0;
141
}
142
143
144
if (tp->mcfg != CFG_METHOD_20 && tp->mcfg != CFG_METHOD_23 &&
145
tp->mcfg != CFG_METHOD_26 && tp->mcfg != CFG_METHOD_27 &&
146
tp->mcfg != CFG_METHOD_28 && tp->mcfg != CFG_METHOD_31 &&
147
- tp->mcfg != CFG_METHOD_32 && tp->mcfg != CFG_METHOD_33) {
148
+ tp->mcfg != CFG_METHOD_32 && tp->mcfg != CFG_METHOD_33 &&
149
+ tp->mcfg != CFG_METHOD_34) {
150
multi_fun_sel_bit = 0;
151
}
152
153
154
if (tp->mcfg == CFG_METHOD_20)
155
multi_fun_sel_bit = 2;
156
else if (tp->mcfg == CFG_METHOD_26 || tp->mcfg == CFG_METHOD_31 ||
157
- tp->mcfg == CFG_METHOD_32 || tp->mcfg == CFG_METHOD_33)
158
+ tp->mcfg == CFG_METHOD_32 || tp->mcfg == CFG_METHOD_33 ||
159
+ tp->mcfg == CFG_METHOD_34)
160
multi_fun_sel_bit = 1;
161
else
162
multi_fun_sel_bit = 0;
163
164
if (tp->mcfg == CFG_METHOD_20)
165
multi_fun_sel_bit = 2;
166
else if (tp->mcfg == CFG_METHOD_26 || tp->mcfg == CFG_METHOD_31 ||
167
- tp->mcfg == CFG_METHOD_32 || tp->mcfg == CFG_METHOD_33)
168
+ tp->mcfg == CFG_METHOD_32 || tp->mcfg == CFG_METHOD_33 ||
169
+ tp->mcfg == CFG_METHOD_34)
170
multi_fun_sel_bit = 1;
171
else
172
multi_fun_sel_bit = 0;
173
174
175
if (tp->mcfg == CFG_METHOD_20 || tp->mcfg == CFG_METHOD_26 ||
176
tp->mcfg == CFG_METHOD_31 || tp->mcfg == CFG_METHOD_32 ||
177
- tp->mcfg == CFG_METHOD_33) {
178
+ tp->mcfg == CFG_METHOD_33 || tp->mcfg == CFG_METHOD_34) {
179
u32 TmpUlong;
180
u16 RegAlignAddr;
181
u8 ShiftByte;
182
183
{
184
if (tp->mcfg == CFG_METHOD_20 || tp->mcfg == CFG_METHOD_26 ||
185
tp->mcfg == CFG_METHOD_31 || tp->mcfg == CFG_METHOD_32 ||
186
- tp->mcfg == CFG_METHOD_33) {
187
+ tp->mcfg == CFG_METHOD_33 || tp->mcfg == CFG_METHOD_34) {
188
u32 TmpUlong;
189
u16 RegAlignAddr;
190
u8 ShiftByte;
191
192
case CFG_METHOD_31:
193
case CFG_METHOD_32:
194
case CFG_METHOD_33:
195
+ case CFG_METHOD_34:
196
//0: BMC, 1: NIC, 2: TCR, 3: VGA/PCIE_TO_USB, 4: EHCI, 5: WIFI, 6: WIFI, 7: KCS
197
if (i == 5 || i == 6) {
198
if (tp->DASH) {
199
200
case CFG_METHOD_31:
201
case CFG_METHOD_32:
202
case CFG_METHOD_33:
203
+ case CFG_METHOD_34:
204
+ case CFG_METHOD_35:
205
RTL_W8(tp, 0xF2, RTL_R8(tp, 0xF2) | BIT_3);
206
mdelay(2);
207
break;
208
209
case CFG_METHOD_31:
210
case CFG_METHOD_32:
211
case CFG_METHOD_33:
212
+ case CFG_METHOD_34:
213
+ case CFG_METHOD_35:
214
RTL_W8(tp, 0xF2, RTL_R8(tp, 0xF2) & ~BIT_3);
215
mdelay(2);
216
break;
217
218
case CFG_METHOD_31:
219
case CFG_METHOD_32:
220
case CFG_METHOD_33:
221
+ case CFG_METHOD_34:
222
+ case CFG_METHOD_35:
223
for (i = 0; i < 10; i++) {
224
udelay(100);
225
if (RTL_R32(tp, TxConfig) & BIT_11)
226
227
case CFG_METHOD_31:
228
case CFG_METHOD_32:
229
case CFG_METHOD_33:
230
+ case CFG_METHOD_34:
231
rtl8168_set_dash_other_fun_dev_aspm_clkreq(tp, 3, 1, 0xFC);
232
rtl8168_set_dash_other_fun_dev_state_change(tp, 3, 0xFC);
233
break;
234
235
case CFG_METHOD_31:
236
case CFG_METHOD_32:
237
case CFG_METHOD_33:
238
+ case CFG_METHOD_34:
239
rtl8168_set_dash_other_fun_dev_state_change(tp, 3, 0xFD);
240
break;
241
}
242
243
case CFG_METHOD_31:
244
case CFG_METHOD_32:
245
case CFG_METHOD_33:
246
+ case CFG_METHOD_34:
247
+ case CFG_METHOD_35:
248
mdelay(2);
249
break;
250
default:
251
252
case CFG_METHOD_31:
253
case CFG_METHOD_32:
254
case CFG_METHOD_33:
255
+ case CFG_METHOD_34:
256
+ case CFG_METHOD_35:
257
RTL_W32(tp, TimeInt1, 0x0000);
258
RTL_W32(tp, TimeInt2, 0x0000);
259
RTL_W32(tp, TimeInt3, 0x0000);
260
261
case CFG_METHOD_31:
262
case CFG_METHOD_32:
263
case CFG_METHOD_33:
264
+ case CFG_METHOD_34:
265
+ case CFG_METHOD_35:
266
csi_tmp = rtl8168_eri_read(tp, 0x1EA, 1, ERIAR_ExGMAC);
267
csi_tmp |= BIT_0;
268
rtl8168_eri_write(tp, 0x1EA, 1, csi_tmp, ERIAR_ExGMAC);
269
270
csi_tmp |= (BIT_10 | BIT_11);
271
rtl8168_eri_write(tp, 0xD4, 4, csi_tmp, ERIAR_ExGMAC);
272
break;
273
- case CFG_METHOD_21 ... CFG_METHOD_33:
274
+ case CFG_METHOD_21 ... CFG_METHOD_34:
275
csi_tmp = rtl8168_eri_read(tp, 0xD4, 4, ERIAR_ExGMAC);
276
csi_tmp |= (BIT_7 | BIT_8 | BIT_9 | BIT_10 | BIT_11 | BIT_12);
277
rtl8168_eri_write(tp, 0xD4, 4, csi_tmp, ERIAR_ExGMAC);
278
279
csi_tmp &= ~(BIT_10 | BIT_11);
280
rtl8168_eri_write(tp, 0xD4, 4, csi_tmp, ERIAR_ExGMAC);
281
break;
282
- case CFG_METHOD_21 ... CFG_METHOD_33:
283
+ case CFG_METHOD_21 ... CFG_METHOD_34:
284
csi_tmp = rtl8168_eri_read(tp, 0xD4, 4, ERIAR_ExGMAC);
285
csi_tmp &= ~(BIT_7 | BIT_8 | BIT_9 | BIT_10 | BIT_11 | BIT_12);
286
rtl8168_eri_write(tp, 0xD4, 4, csi_tmp, ERIAR_ExGMAC);
287
288
int link_status_on;
289
290
#ifdef ENABLE_FIBER_SUPPORT
291
- rtl8168_check_fiber_link_status(dev);
292
+ rtl8168_check_fiber_link_status(tp);
293
#endif //ENABLE_FIBER_SUPPORT
294
295
link_status_on = tp->link_ok(dev);
296
297
tp->mcfg == CFG_METHOD_27 || tp->mcfg == CFG_METHOD_28 ||
298
tp->mcfg == CFG_METHOD_29 || tp->mcfg == CFG_METHOD_30 ||
299
tp->mcfg == CFG_METHOD_31 || tp->mcfg == CFG_METHOD_32 ||
300
- tp->mcfg == CFG_METHOD_33) && netif_running(dev)) {
301
+ tp->mcfg == CFG_METHOD_33 || tp->mcfg == CFG_METHOD_34 ||
302
+ tp->mcfg == CFG_METHOD_35) &&
303
+ netif_running(dev)) {
304
if (RTL_R8(tp, PHYstatus)&FullDup)
305
RTL_W32(tp, TxConfig, (RTL_R32(tp, TxConfig) | (BIT_24 | BIT_25)) & ~BIT_19);
306
else
307
308
if (tp->mcfg == CFG_METHOD_21 || tp->mcfg == CFG_METHOD_22 ||
309
tp->mcfg == CFG_METHOD_27 || tp->mcfg == CFG_METHOD_28 ||
310
tp->mcfg == CFG_METHOD_31 || tp->mcfg == CFG_METHOD_32 ||
311
- tp->mcfg == CFG_METHOD_33) {
312
+ tp->mcfg == CFG_METHOD_33 || tp->mcfg == CFG_METHOD_34) {
313
/*half mode*/
314
if (!(RTL_R8(tp, PHYstatus)&FullDup)) {
315
rtl8168_mdio_write(tp, 0x1F, 0x0000);
316
317
}
318
319
if ((tp->mcfg == CFG_METHOD_31 || tp->mcfg == CFG_METHOD_32 ||
320
- tp->mcfg == CFG_METHOD_33) && (RTL_R8(tp, PHYstatus) & _10bps)) {
321
+ tp->mcfg == CFG_METHOD_33 || tp->mcfg == CFG_METHOD_34) &&
322
+ (RTL_R8(tp, PHYstatus) & _10bps)) {
323
u32 csi_tmp;
324
325
csi_tmp = rtl8168_eri_read(tp, 0x1D0, 1, ERIAR_ExGMAC);
326
327
case CFG_METHOD_25:
328
case CFG_METHOD_27:
329
case CFG_METHOD_28:
330
+ case CFG_METHOD_31:
331
+ case CFG_METHOD_32:
332
+ case CFG_METHOD_33:
333
+ case CFG_METHOD_34:
334
if (tp->org_pci_offset_99 & BIT_2)
335
tp->issue_offset_99_event = TRUE;
336
break;
337
338
case CFG_METHOD_25:
339
case CFG_METHOD_27:
340
case CFG_METHOD_28:
341
+ case CFG_METHOD_31:
342
+ case CFG_METHOD_32:
343
+ case CFG_METHOD_33:
344
+ case CFG_METHOD_34:
345
if (tp->issue_offset_99_event) {
346
if (!(RTL_R8(tp, PHYstatus) & PowerSaveStatus)) {
347
tp->issue_offset_99_event = FALSE;
348
349
tp->mcfg == CFG_METHOD_27 || tp->mcfg == CFG_METHOD_28 ||
350
tp->mcfg == CFG_METHOD_29 || tp->mcfg == CFG_METHOD_30 ||
351
tp->mcfg == CFG_METHOD_31 || tp->mcfg == CFG_METHOD_32 ||
352
- tp->mcfg == CFG_METHOD_33) {
353
+ tp->mcfg == CFG_METHOD_33 || tp->mcfg == CFG_METHOD_34 ||
354
+ tp->mcfg == CFG_METHOD_35) {
355
val = rtl8168_mdio_read_phy_ocp(tp, 0x0C41, 0x13);
356
if (val != 0x0050) {
357
rtl8168_set_phy_mcu_patch_request(tp);
358
359
tp->mcfg == CFG_METHOD_27 || tp->mcfg == CFG_METHOD_28 ||
360
tp->mcfg == CFG_METHOD_29 || tp->mcfg == CFG_METHOD_30 ||
361
tp->mcfg == CFG_METHOD_31 || tp->mcfg == CFG_METHOD_32 ||
362
- tp->mcfg == CFG_METHOD_33) {
363
+ tp->mcfg == CFG_METHOD_33 || tp->mcfg == CFG_METHOD_34 ||
364
+ tp->mcfg == CFG_METHOD_35) {
365
val = rtl8168_mdio_read_phy_ocp(tp, 0x0C41, 0x13);
366
if (val != 0x0500) {
367
rtl8168_set_phy_mcu_patch_request(tp);
368
369
case CFG_METHOD_31:
370
case CFG_METHOD_32:
371
case CFG_METHOD_33:
372
+ case CFG_METHOD_34:
373
+ case CFG_METHOD_35:
374
csi_tmp = rtl8168_eri_read(tp, 0x3F2, 2, ERIAR_ExGMAC);
375
csi_tmp &= ~(BIT_0 | BIT_1);
376
rtl8168_eri_write(tp, 0x3F2, 2, csi_tmp, ERIAR_ExGMAC);
377
378
case CFG_METHOD_31:
379
case CFG_METHOD_32:
380
case CFG_METHOD_33:
381
+ case CFG_METHOD_34:
382
+ case CFG_METHOD_35:
383
rtl8168_csi_fun0_write_byte(tp, 0x99, 0x00);
384
break;
385
}
386
387
case CFG_METHOD_31:
388
case CFG_METHOD_32:
389
case CFG_METHOD_33:
390
+ case CFG_METHOD_34:
391
+ case CFG_METHOD_35:
392
rtl8168_csi_fun0_write_byte(tp, 0x99, tp->org_pci_offset_99);
393
break;
394
}
395
396
case CFG_METHOD_31:
397
case CFG_METHOD_32:
398
case CFG_METHOD_33:
399
+ case CFG_METHOD_34:
400
+ case CFG_METHOD_35:
401
csi_tmp = rtl8168_eri_read(tp, 0x3F2, 2, ERIAR_ExGMAC);
402
csi_tmp &= ~(BIT_0 | BIT_1);
403
if (tp->org_pci_offset_99 & (BIT_5 | BIT_6))
404
405
case CFG_METHOD_31:
406
case CFG_METHOD_32:
407
case CFG_METHOD_33:
408
+ case CFG_METHOD_34:
409
+ case CFG_METHOD_35:
410
csi_tmp = rtl8168_eri_read(tp, 0x3F2, 2, ERIAR_ExGMAC);
411
csi_tmp &= ~( BIT_8 | BIT_9 | BIT_10 | BIT_11 | BIT_12 | BIT_13 | BIT_14 | BIT_15 );
412
csi_tmp |= ( BIT_9 | BIT_10 | BIT_13 | BIT_14 | BIT_15 );
413
414
case CFG_METHOD_31:
415
case CFG_METHOD_32:
416
case CFG_METHOD_33:
417
+ case CFG_METHOD_34:
418
+ case CFG_METHOD_35:
419
if (tp->org_pci_offset_99 & BIT_2)
420
rtl8168_mac_ocp_write(tp, 0xE0A2, rtl8168_mac_ocp_read(tp, 0xE0A2) | BIT_0);
421
break;
422
423
case CFG_METHOD_31:
424
case CFG_METHOD_32:
425
case CFG_METHOD_33:
426
+ case CFG_METHOD_34:
427
+ case CFG_METHOD_35:
428
rtl8168_eri_write(tp, 0x2E8, 2, 0x9003, ERIAR_ExGMAC);
429
rtl8168_eri_write(tp, 0x2EA, 2, 0x9003, ERIAR_ExGMAC);
430
rtl8168_eri_write(tp, 0x2EC, 2, 0x9003, ERIAR_ExGMAC);
431
432
case CFG_METHOD_26:
433
case CFG_METHOD_29:
434
case CFG_METHOD_30:
435
+ case CFG_METHOD_35:
436
if (tp->org_pci_offset_99 & BIT_2)
437
RTL_W8(tp, 0xB6, RTL_R8(tp, 0xB6) | BIT_0);
438
break;
439
440
case CFG_METHOD_31:
441
case CFG_METHOD_32:
442
case CFG_METHOD_33:
443
+ case CFG_METHOD_34:
444
+ case CFG_METHOD_35:
445
csi_tmp = rtl8168_eri_read(tp, 0x1E2, 1, ERIAR_ExGMAC);
446
csi_tmp &= ~BIT_2;
447
rtl8168_eri_write(tp, 0x1E2, 1, csi_tmp, ERIAR_ExGMAC);
448
449
case CFG_METHOD_31:
450
case CFG_METHOD_32:
451
case CFG_METHOD_33:
452
+ case CFG_METHOD_34:
453
csi_tmp = rtl8168_eri_read(tp, 0x1E8, 4, ERIAR_ExGMAC);
454
csi_tmp &= ~(0x0000FFF0);
455
csi_tmp |= (0x00000640);
456
457
}
458
459
switch (tp->mcfg) {
460
+ case CFG_METHOD_35:
461
+ csi_tmp = rtl8168_eri_read(tp, 0x1E8, 2, ERIAR_ExGMAC);
462
+ csi_tmp &= ~(0xFFF0);
463
+ csi_tmp |= 0x0640;
464
+ rtl8168_eri_write(tp,0x1E8, 2, csi_tmp, ERIAR_ExGMAC);
465
+
466
+ csi_tmp = rtl8168_eri_read(tp, 0x1E4, 2, ERIAR_ExGMAC);
467
+ csi_tmp &= ~(0xFF00);
468
+ rtl8168_eri_write(tp, 0x1E4, 2, csi_tmp, ERIAR_ExGMAC);
469
+ break;
470
+ }
471
+
472
+ switch (tp->mcfg) {
473
case CFG_METHOD_24:
474
case CFG_METHOD_25:
475
case CFG_METHOD_26:
476
477
case CFG_METHOD_28:
478
case CFG_METHOD_29:
479
case CFG_METHOD_30:
480
+ case CFG_METHOD_35:
481
csi_tmp = rtl8168_eri_read(tp, 0x1E2, 1, ERIAR_ExGMAC);
482
csi_tmp |= BIT_2;
483
rtl8168_eri_write(tp, 0x1E2, 1, csi_tmp, ERIAR_ExGMAC);
484
485
case CFG_METHOD_31:
486
case CFG_METHOD_32:
487
case CFG_METHOD_33:
488
- rtl8168_issue_offset_99_event(tp);
489
- break;
490
- }
491
-
492
- switch (tp->mcfg) {
493
- case CFG_METHOD_21:
494
- case CFG_METHOD_22:
495
- case CFG_METHOD_23:
496
- case CFG_METHOD_24:
497
- case CFG_METHOD_25:
498
- case CFG_METHOD_26:
499
- case CFG_METHOD_27:
500
- case CFG_METHOD_28:
501
- case CFG_METHOD_29:
502
- case CFG_METHOD_30:
503
- case CFG_METHOD_31:
504
- case CFG_METHOD_32:
505
- case CFG_METHOD_33:
506
+ case CFG_METHOD_34:
507
+ case CFG_METHOD_35:
508
+ if (tp->org_pci_offset_99 & BIT_2)
509
+ rtl8168_issue_offset_99_event(tp);
510
rtl8168_disable_pci_offset_99(tp);
511
break;
512
}
513
+
514
switch (tp->mcfg) {
515
case CFG_METHOD_24:
516
case CFG_METHOD_25:
517
518
case CFG_METHOD_31:
519
case CFG_METHOD_32:
520
case CFG_METHOD_33:
521
+ case CFG_METHOD_34:
522
+ case CFG_METHOD_35:
523
rtl8168_disable_pci_offset_180(tp);
524
break;
525
}
526
527
if (tp->mcfg == CFG_METHOD_21 || tp->mcfg == CFG_METHOD_22 ||
528
tp->mcfg == CFG_METHOD_23 || tp->mcfg == CFG_METHOD_24 ||
529
tp->mcfg == CFG_METHOD_25 || tp->mcfg == CFG_METHOD_26 ||
530
- tp->mcfg == CFG_METHOD_27 || tp->mcfg == CFG_METHOD_28 ||
531
- tp->mcfg == CFG_METHOD_31 || tp->mcfg == CFG_METHOD_32 ||
532
- tp->mcfg == CFG_METHOD_33) {
533
+ tp->mcfg == CFG_METHOD_27 || tp->mcfg == CFG_METHOD_28)
534
rtl8168_eri_write(tp, 0x2F8, 2, 0x0064, ERIAR_ExGMAC);
535
- }
536
537
if (tp->bios_setting & BIT_28) {
538
if (tp->mcfg == CFG_METHOD_18 || tp->mcfg == CFG_METHOD_19 ||
539
540
541
rtl8168_set_pci_99_180_exit_driver_para(dev);
542
543
+ switch (tp->mcfg) {
544
+ case CFG_METHOD_35:
545
+ rtl8168_set_mcu_ocp_bit(tp, 0xD438, BIT_3);
546
+ rtl8168_set_mcu_ocp_bit(tp, 0xDE38, BIT_2);
547
+ rtl8168_clear_mcu_ocp_bit(tp, 0xDE28, (BIT_1 | BIT_0));
548
+ rtl8168_set_mcu_ocp_bit(tp, 0xD438, (BIT_1 | BIT_0));
549
+ break;
550
+ }
551
+
552
/*disable ocp phy power saving*/
553
if (tp->mcfg == CFG_METHOD_25 || tp->mcfg == CFG_METHOD_26 ||
554
tp->mcfg == CFG_METHOD_27 || tp->mcfg == CFG_METHOD_28 ||
555
tp->mcfg == CFG_METHOD_29 || tp->mcfg == CFG_METHOD_30 ||
556
tp->mcfg == CFG_METHOD_31 || tp->mcfg == CFG_METHOD_32 ||
557
- tp->mcfg == CFG_METHOD_33)
558
+ tp->mcfg == CFG_METHOD_33 || tp->mcfg == CFG_METHOD_34 ||
559
+ tp->mcfg == CFG_METHOD_35)
560
if (!tp->dash_printer_enabled)
561
rtl8168_disable_ocp_phy_power_saving(dev);
562
563
564
tp->mcfg == CFG_METHOD_27 || tp->mcfg == CFG_METHOD_28 ||
565
tp->mcfg == CFG_METHOD_29 || tp->mcfg == CFG_METHOD_30 ||
566
tp->mcfg == CFG_METHOD_31 || tp->mcfg == CFG_METHOD_32 ||
567
- tp->mcfg == CFG_METHOD_33) {
568
+ tp->mcfg == CFG_METHOD_33 || tp->mcfg == CFG_METHOD_34 ||
569
+ tp->mcfg == CFG_METHOD_35) {
570
rtl8168_enable_cfg9346_write(tp);
571
RTL_W8(tp, Config2, RTL_R8(tp, Config2) | PMSTS_En);
572
rtl8168_disable_cfg9346_write(tp);
573
574
case CFG_METHOD_31:
575
case CFG_METHOD_32:
576
case CFG_METHOD_33:
577
+ case CFG_METHOD_34:
578
+ case CFG_METHOD_35:
579
RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~BIT_7);
580
break;
581
}
582
583
case CFG_METHOD_14 ... CFG_METHOD_15:
584
RTL_W8(tp, 0xD0, RTL_R8(tp, 0xD0) & ~BIT_6);
585
break;
586
- case CFG_METHOD_16 ... CFG_METHOD_33:
587
+ case CFG_METHOD_16 ... CFG_METHOD_34:
588
RTL_W8(tp, 0xD0, RTL_R8(tp, 0xD0) & ~BIT_6);
589
RTL_W8(tp, 0xF2, RTL_R8(tp, 0xF2) & ~BIT_6);
590
break;
591
592
case CFG_METHOD_31:
593
case CFG_METHOD_32:
594
case CFG_METHOD_33:
595
+ case CFG_METHOD_34:
596
+ case CFG_METHOD_35:
597
RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | BIT_7 | BIT_6);
598
break;
599
}
600
601
602
if (tp->mcfg == CFG_METHOD_29 || tp->mcfg == CFG_METHOD_30 ||
603
tp->mcfg == CFG_METHOD_31 || tp->mcfg == CFG_METHOD_32 ||
604
- tp->mcfg == CFG_METHOD_33) {
605
+ tp->mcfg == CFG_METHOD_33 || tp->mcfg == CFG_METHOD_34 ||
606
+ tp->mcfg == CFG_METHOD_35) {
607
//Disable Giga Lite
608
rtl8168_mdio_write(tp, 0x1F, 0x0A42);
609
rtl8168_clear_eth_phy_bit(tp, 0x14, BIT_9);
610
if (tp->mcfg == CFG_METHOD_31 || tp->mcfg == CFG_METHOD_32 ||
611
- tp->mcfg == CFG_METHOD_33)
612
+ tp->mcfg == CFG_METHOD_33 || tp->mcfg == CFG_METHOD_34)
613
rtl8168_clear_eth_phy_bit(tp, 0x14, BIT_7);
614
rtl8168_mdio_write(tp, 0x1F, 0x0A40);
615
rtl8168_mdio_write(tp, 0x1F, 0x0000);
616
617
giga_ctrl |= ADVERTISE_1000FULL;
618
619
//flow control
620
- if (dev->mtu <= ETH_DATA_LEN)
621
+ if (dev->mtu <= ETH_DATA_LEN && tp->fcpause == rtl8168_fc_full)
622
auto_nego |= ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM;
623
624
tp->phy_auto_nego_reg = auto_nego;
625
626
spin_unlock_irqrestore(&tp->lock, flags);
627
}
628
629
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
630
+static void rtl8168_get_pauseparam(struct net_device *dev,
631
+ struct ethtool_pauseparam *pause)
632
+{
633
+ struct rtl8168_private *tp = netdev_priv(dev);
634
+
635
+ pause->autoneg = (tp->autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE);
636
+ if (tp->fcpause == rtl8168_fc_rx_pause)
637
+ pause->rx_pause = 1;
638
+ else if (tp->fcpause == rtl8168_fc_tx_pause)
639
+ pause->tx_pause = 1;
640
+ else if (tp->fcpause == rtl8168_fc_full) {
641
+ pause->rx_pause = 1;
642
+ pause->tx_pause = 1;
643
+ }
644
+}
645
+
646
+static int rtl8168_set_pauseparam(struct net_device *dev,
647
+ struct ethtool_pauseparam *pause)
648
+{
649
+ struct rtl8168_private *tp = netdev_priv(dev);
650
+ enum rtl8168_fc_mode newfc;
651
+
652
+ if (pause->tx_pause || pause->rx_pause)
653
+ newfc = rtl8168_fc_full;
654
+ else
655
+ newfc = rtl8168_fc_none;
656
+
657
+ if (tp->fcpause != newfc) {
658
+ tp->fcpause = newfc;
659
+
660
+ rtl8168_set_speed(dev, tp->autoneg, tp->speed, tp->duplex, tp->advertising);
661
+ }
662
+
663
+ return 0;
664
+
665
+}
666
+#endif //LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
667
+
668
static u32
669
rtl8168_get_msglevel(struct net_device *dev)
670
{
671
672
return -EOPNOTSUPP;
673
}
674
}
675
+#endif //LINUX_VERSION_CODE < KERNEL_VERSION(2,6,33)
676
+
677
+static void
678
+rtl8168_wait_for_quiescence(struct net_device *dev)
679
+{
680
+ struct rtl8168_private *tp = netdev_priv(dev);
681
+
682
+ synchronize_irq(dev->irq);
683
+
684
+ /* Wait for any pending NAPI task to complete */
685
+#ifdef CONFIG_R8168_NAPI
686
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0)
687
+ RTL_NAPI_DISABLE(dev, &tp->napi);
688
#endif
689
+#endif //CONFIG_R8168_NAPI
690
+
691
+ rtl8168_irq_mask_and_ack(tp);
692
+
693
+#ifdef CONFIG_R8168_NAPI
694
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0)
695
+ RTL_NAPI_ENABLE(dev, &tp->napi);
696
+#endif
697
+#endif //CONFIG_R8168_NAPI
698
+}
699
+
700
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
701
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,17,0)
702
+static void rtl8168_get_ringparam(struct net_device *dev,
703
+ struct ethtool_ringparam *ring,
704
+ struct kernel_ethtool_ringparam *kernel_ring,
705
+ struct netlink_ext_ack *extack)
706
+#else
707
+static void rtl8168_get_ringparam(struct net_device *dev,
708
+ struct ethtool_ringparam *ring)
709
+#endif //LINUX_VERSION_CODE >= KERNEL_VERSION(5,17,0)
710
+{
711
+ struct rtl8168_private *tp = netdev_priv(dev);
712
+
713
+ ring->rx_max_pending = MAX_NUM_TX_DESC;
714
+ ring->tx_max_pending = MAX_NUM_RX_DESC;;
715
+ ring->rx_pending = tp->num_rx_desc;
716
+ ring->tx_pending = tp->num_tx_desc;
717
+}
718
+
719
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,17,0)
720
+static int rtl8168_set_ringparam(struct net_device *dev,
721
+ struct ethtool_ringparam *ring,
722
+ struct kernel_ethtool_ringparam *kernel_ring,
723
+ struct netlink_ext_ack *extack)
724
+#else
725
+static int rtl8168_set_ringparam(struct net_device *dev,
726
+ struct ethtool_ringparam *ring)
727
+#endif //LINUX_VERSION_CODE >= KERNEL_VERSION(5,17,0)
728
+{
729
+ struct rtl8168_private *tp = netdev_priv(dev);
730
+ u32 new_rx_count, new_tx_count;
731
+ int rc = 0;
732
+
733
+ if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
734
+ return -EINVAL;
735
+
736
+ new_tx_count = clamp_t(u32, ring->tx_pending,
737
+ MIN_NUM_TX_DESC, MAX_NUM_TX_DESC);
738
+
739
+ new_rx_count = clamp_t(u32, ring->rx_pending,
740
+ MIN_NUM_RX_DESC, MAX_NUM_RX_DESC);
741
+
742
+ if ((new_rx_count == tp->num_rx_desc) &&
743
+ (new_tx_count == tp->num_tx_desc)) {
744
+ /* nothing to do */
745
+ return 0;
746
+ }
747
+
748
+ if (netif_running(dev)) {
749
+ rtl8168_wait_for_quiescence(dev);
750
+ rtl8168_close(dev);
751
+ }
752
+
753
+ tp->num_rx_desc = new_rx_count;
754
+ tp->num_tx_desc = new_tx_count;
755
+
756
+ if (netif_running(dev))
757
+ rc = rtl8168_open(dev);
758
+
759
+ return rc;
760
+}
761
+#endif //LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
762
763
#if LINUX_VERSION_CODE > KERNEL_VERSION(2,4,22)
764
static void
765
766
{
767
switch (stringset) {
768
case ETH_SS_STATS:
769
- memcpy(data, *rtl8168_gstrings, sizeof(rtl8168_gstrings));
770
+ memcpy(data, rtl8168_gstrings, sizeof(rtl8168_gstrings));
771
break;
772
}
773
}
774
-#endif //#LINUX_VERSION_CODE > KERNEL_VERSION(2,4,22)
775
+#endif //LINUX_VERSION_CODE > KERNEL_VERSION(2,4,22)
776
777
static int rtl_get_eeprom_len(struct net_device *dev)
778
{
779
780
case CFG_METHOD_31:
781
case CFG_METHOD_32:
782
case CFG_METHOD_33:
783
+ case CFG_METHOD_34:
784
+ case CFG_METHOD_35:
785
csi_tmp = rtl8168_eri_read(tp, 0x1B0, 4, ERIAR_ExGMAC);
786
csi_tmp |= BIT_1 | BIT_0;
787
rtl8168_eri_write(tp, 0x1B0, 4, csi_tmp, ERIAR_ExGMAC);
788
789
case CFG_METHOD_31:
790
case CFG_METHOD_32:
791
case CFG_METHOD_33:
792
+ case CFG_METHOD_34:
793
+ case CFG_METHOD_35:
794
rtl8168_mdio_write(tp, 0x1F, 0x0A4A);
795
rtl8168_set_eth_phy_bit(tp, 0x11, BIT_9);
796
rtl8168_mdio_write(tp, 0x1F, 0x0A42);
797
798
case CFG_METHOD_31:
799
case CFG_METHOD_32:
800
case CFG_METHOD_33:
801
+ case CFG_METHOD_34:
802
rtl8168_oob_mutex_lock(tp);
803
break;
804
}
805
806
case CFG_METHOD_31:
807
case CFG_METHOD_32:
808
case CFG_METHOD_33:
809
+ case CFG_METHOD_34:
810
+ case CFG_METHOD_35:
811
rtl8168_set_phy_mcu_patch_request(tp);
812
break;
813
}
814
815
break;
816
case CFG_METHOD_29:
817
case CFG_METHOD_30:
818
+ case CFG_METHOD_35:
819
data = rtl8168_mac_ocp_read(tp, 0xE052);
820
data &= ~(BIT_0);
821
rtl8168_mac_ocp_write(tp, 0xE052, data);
822
823
case CFG_METHOD_31:
824
case CFG_METHOD_32:
825
case CFG_METHOD_33:
826
- /*
827
+ case CFG_METHOD_34:
828
data = rtl8168_mac_ocp_read(tp, 0xE052);
829
- data |= BIT_0;
830
+ data &= ~(BIT_0);
831
+ if (tp->HwPkgDet == 0x0F)
832
+ data |= BIT_0;
833
rtl8168_mac_ocp_write(tp, 0xE052, data);
834
- */
835
836
rtl8168_mdio_write(tp, 0x1F, 0x0A43);
837
data = rtl8168_mdio_read(tp, 0x10) | BIT_15;
838
839
case CFG_METHOD_31:
840
case CFG_METHOD_32:
841
case CFG_METHOD_33:
842
+ case CFG_METHOD_34:
843
+ case CFG_METHOD_35:
844
rtl8168_clear_phy_mcu_patch_request(tp);
845
break;
846
}
847
848
case CFG_METHOD_31:
849
case CFG_METHOD_32:
850
case CFG_METHOD_33:
851
+ case CFG_METHOD_34:
852
rtl8168_oob_mutex_unlock(tp);
853
break;
854
}
855
856
case CFG_METHOD_31:
857
case CFG_METHOD_32:
858
case CFG_METHOD_33:
859
+ case CFG_METHOD_34:
860
+ case CFG_METHOD_35:
861
csi_tmp = rtl8168_eri_read(tp, 0x1B0, 4, ERIAR_ExGMAC);
862
csi_tmp &= ~(BIT_1 | BIT_0);
863
rtl8168_eri_write(tp, 0x1B0, 4, csi_tmp, ERIAR_ExGMAC);
864
865
switch (tp->mcfg) {
866
case CFG_METHOD_29:
867
case CFG_METHOD_30:
868
+ case CFG_METHOD_35:
869
rtl8168_mdio_write(tp, 0x1F, 0x0A42);
870
rtl8168_clear_eth_phy_bit(tp, 0x14, BIT_7);
871
rtl8168_mdio_write(tp, 0x1F, 0x0A4A);
872
873
case CFG_METHOD_31:
874
case CFG_METHOD_32:
875
case CFG_METHOD_33:
876
+ case CFG_METHOD_34:
877
rtl8168_oob_mutex_lock(tp);
878
break;
879
}
880
881
case CFG_METHOD_31:
882
case CFG_METHOD_32:
883
case CFG_METHOD_33:
884
+ case CFG_METHOD_34:
885
+ case CFG_METHOD_35:
886
rtl8168_set_phy_mcu_patch_request(tp);
887
break;
888
}
889
890
case CFG_METHOD_31:
891
case CFG_METHOD_32:
892
case CFG_METHOD_33:
893
+ case CFG_METHOD_34:
894
+ case CFG_METHOD_35:
895
data = rtl8168_mac_ocp_read(tp, 0xE052);
896
data &= ~(BIT_0);
897
rtl8168_mac_ocp_write(tp, 0xE052, data);
898
899
case CFG_METHOD_31:
900
case CFG_METHOD_32:
901
case CFG_METHOD_33:
902
+ case CFG_METHOD_34:
903
+ case CFG_METHOD_35:
904
rtl8168_clear_phy_mcu_patch_request(tp);
905
break;
906
}
907
908
case CFG_METHOD_31:
909
case CFG_METHOD_32:
910
case CFG_METHOD_33:
911
+ case CFG_METHOD_34:
912
rtl8168_oob_mutex_unlock(tp);
913
break;
914
}
915
916
u16 val;
917
918
switch (tp->mcfg) {
919
- case CFG_METHOD_21 ... CFG_METHOD_33:
920
+ case CFG_METHOD_21 ... CFG_METHOD_34:
921
break;
922
default:
923
return -EOPNOTSUPP;
924
925
unsigned long flags;
926
927
switch (tp->mcfg) {
928
- case CFG_METHOD_21 ... CFG_METHOD_33:
929
+ case CFG_METHOD_21 ... CFG_METHOD_34:
930
break;
931
default:
932
return -EOPNOTSUPP;
933
934
static const struct ethtool_ops rtl8168_ethtool_ops = {
935
.get_drvinfo = rtl8168_get_drvinfo,
936
.get_regs_len = rtl8168_get_regs_len,
937
- .get_link = ethtool_op_get_link,
938
+ .get_link = ethtool_op_get_link,
939
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
940
+ .get_ringparam = rtl8168_get_ringparam,
941
+ .set_ringparam = rtl8168_set_ringparam,
942
+#endif //LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
943
#if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0)
944
.get_settings = rtl8168_get_settings,
945
.set_settings = rtl8168_set_settings,
946
#else
947
.get_link_ksettings = rtl8168_get_settings,
948
.set_link_ksettings = rtl8168_set_settings,
949
-#endif
950
+#endif //LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0)
951
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
952
+ .get_pauseparam = rtl8168_get_pauseparam,
953
+ .set_pauseparam = rtl8168_set_pauseparam,
954
+#endif //LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
955
.get_msglevel = rtl8168_get_msglevel,
956
.set_msglevel = rtl8168_set_msglevel,
957
#if LINUX_VERSION_CODE < KERNEL_VERSION(3,3,0)
958
959
#ifdef NETIF_F_TSO
960
.get_tso = ethtool_op_get_tso,
961
.set_tso = ethtool_op_set_tso,
962
-#endif
963
-#endif
964
+#endif //NETIF_F_TSO
965
+#endif //LINUX_VERSION_CODE < KERNEL_VERSION(3,3,0)
966
.get_regs = rtl8168_get_regs,
967
.get_wol = rtl8168_get_wol,
968
.set_wol = rtl8168_set_wol,
969
970
.get_stats_count = rtl8168_get_stats_count,
971
#else
972
.get_sset_count = rtl8168_get_sset_count,
973
-#endif
974
+#endif //LINUX_VERSION_CODE < KERNEL_VERSION(2,6,33)
975
.get_ethtool_stats = rtl8168_get_ethtool_stats,
976
#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23)
977
#ifdef ETHTOOL_GPERMADDR
978
979
case CFG_METHOD_31:
980
case CFG_METHOD_32:
981
case CFG_METHOD_33:
982
+ case CFG_METHOD_34:
983
+ case CFG_METHOD_35:
984
rtl8168_mdio_write(tp, 0x1F, 0x0A43);
985
rtl8168_mdio_write(tp, 0x13, 0x8045);
986
rtl8168_mdio_write(tp, 0x14, 0x0000);
987
988
case CFG_METHOD_31:
989
case CFG_METHOD_32:
990
case CFG_METHOD_33:
991
+ case CFG_METHOD_34:
992
+ case CFG_METHOD_35:
993
rtl8168_mdio_write(tp, 0x1F, 0x0A43);
994
rtl8168_mdio_write(tp, 0x13, 0x8045);
995
rtl8168_mdio_write(tp, 0x14, 0x2444);
996
997
tp->HwIcVerUnknown = TRUE;
998
}
999
1000
+ if (tp->mcfg == CFG_METHOD_30 &&
1001
+ (rtl8168_mac_ocp_read(tp, 0xD006) & 0xFF00) == 0x0100)
1002
+ tp->mcfg = CFG_METHOD_35;
1003
+
1004
tp->efuse_ver = EFUSE_SUPPORT_V3;
1005
break;
1006
case 0x54800000:
1007
1008
tp->mcfg = CFG_METHOD_32;
1009
} else if (ICVerID == 0x00300000) {
1010
tp->mcfg = CFG_METHOD_33;
1011
+ } else if (ICVerID == 0x00400000) {
1012
+ tp->mcfg = CFG_METHOD_34;
1013
} else {
1014
- tp->mcfg = CFG_METHOD_33;
1015
+ tp->mcfg = CFG_METHOD_34;
1016
tp->HwIcVerUnknown = TRUE;
1017
}
1018
1019
1020
1021
static
1022
bool
1023
-rtl8168_test_phy_ocp(struct rtl8168_private *tp)
1024
+rtl8168_test_phy_ocp_v2(struct rtl8168_private *tp)
1025
{
1026
bool RestorePhyOcpReg = FALSE;
1027
1028
- if (tp->TestPhyOcpReg == FALSE) goto exit;
1029
+ u16 PhyRegValue;
1030
+ u8 ResetPhyType = 0;
1031
1032
- if (tp->HwSuppEsdVer == 2) {
1033
- u16 PhyRegValue;
1034
- u8 ResetPhyType = 0;
1035
+ if (HW_PHY_STATUS_INI == rtl8168_get_phy_state(tp)) {
1036
+ ResetPhyType = 1;
1037
+ } else {
1038
+ rtl8168_mdio_write(tp, 0x1F, 0x0C40);
1039
+ PhyRegValue = rtl8168_mdio_read(tp, 0x12);
1040
+ rtl8168_mdio_write(tp, 0x1F, 0x0000);
1041
+ if ((PhyRegValue & 0x03) != 0x00) {
1042
+ ResetPhyType = 2;
1043
+ }
1044
+ }
1045
1046
- if (HW_PHY_STATUS_INI == rtl8168_get_phy_state(tp)) {
1047
- ResetPhyType = 1;
1048
- } else {
1049
+ if (ResetPhyType == 0) goto exit;
1050
+
1051
+ netif_err(tp, drv, tp->dev, "test_phy_ocp ResetPhyType = 0x%02x\n.\n",
1052
+ ResetPhyType);
1053
+
1054
+ rtl8168_mdio_write(tp, 0x1F, 0x0C41);
1055
+ rtl8168_set_eth_phy_bit(tp, 0x14, BIT_0);
1056
+ rtl8168_mdio_write(tp, 0x1F, 0x0000);
1057
+ mdelay(24); //24ms
1058
+
1059
+ rtl8168_mdio_write(tp, 0x1F, 0x0C40);
1060
+ PhyRegValue = rtl8168_mdio_read(tp, 0x12);
1061
+ if ((PhyRegValue & 0x03) != 0x00) {
1062
+ u32 WaitCnt = 0;
1063
+ while ((PhyRegValue & 0x03) != 0x00 && WaitCnt < 5) {
1064
+ rtl8168_mdio_write(tp, 0x1F, 0x0C40);
1065
+ rtl8168_set_eth_phy_bit(tp, 0x11, (BIT_15 | BIT_14));
1066
+ rtl8168_clear_eth_phy_bit(tp, 0x11, (BIT_15 | BIT_14));
1067
+ mdelay(100);
1068
rtl8168_mdio_write(tp, 0x1F, 0x0C40);
1069
PhyRegValue = rtl8168_mdio_read(tp, 0x12);
1070
- rtl8168_mdio_write(tp, 0x1F, 0x0000);
1071
- if ((PhyRegValue & 0x03) != 0x00) {
1072
- ResetPhyType = 2;
1073
- }
1074
+ WaitCnt++;
1075
}
1076
+ }
1077
1078
- if (ResetPhyType > 0) {
1079
- u32 WaitCnt;
1080
- struct net_device *dev = tp->dev;
1081
+ rtl8168_mdio_write(tp, 0x1F, 0x0000);
1082
1083
- printk(KERN_ERR "%s: test_phy_ocp ResetPhyType = 0x%02x\n.\n", dev->name, ResetPhyType);
1084
+ rtl8168_mdio_write(tp, 0x1F, 0x0A46);
1085
+ rtl8168_mdio_write(tp, 0x10, tp->BackupPhyFuseDout_15_0);
1086
+ rtl8168_mdio_write(tp, 0x12, tp->BackupPhyFuseDout_47_32);
1087
+ rtl8168_mdio_write(tp, 0x13, tp->BackupPhyFuseDout_63_48);
1088
+ rtl8168_mdio_write(tp, 0x1F, 0x0000);
1089
1090
- rtl8168_mdio_write(tp, 0x1F, 0x0C41);
1091
- rtl8168_set_eth_phy_bit(tp, 0x14, BIT_0);
1092
- rtl8168_mdio_write(tp, 0x1F, 0x0000);
1093
- mdelay(24); //24ms
1094
+ rtl8168_wait_phy_state_ready(tp, HW_PHY_STATUS_INI, 5000000);
1095
+ rtl8168_mdio_write(tp, 0x1F, 0x0A46);
1096
+ rtl8168_set_eth_phy_bit(tp, 0x14, BIT_0);
1097
+ rtl8168_mdio_write(tp, 0x1F, 0x0000);
1098
+ rtl8168_wait_phy_state_ready(tp, HW_PHY_STATUS_LAN_ON, 500000);
1099
+
1100
+ tp->HwHasWrRamCodeToMicroP = FALSE;
1101
+
1102
+ RestorePhyOcpReg = TRUE;
1103
+
1104
+exit:
1105
+ rtl8168_mdio_write(tp, 0x1F, 0x0000);
1106
+
1107
+ return RestorePhyOcpReg;
1108
+}
1109
+
1110
+static
1111
+bool
1112
+rtl8168_test_phy_ocp_v3(struct rtl8168_private *tp)
1113
+{
1114
+ bool RestorePhyOcpReg = FALSE;
1115
+
1116
+ u16 PhyRegValue;
1117
+ u8 ResetPhyType = 0;
1118
+ u8 watch_dog = 0;
1119
+ u8 uc_response;
1120
+ u8 nctl_pc_range_fail;
1121
+ u8 nctl_pc_stuck_fail;
1122
+
1123
+ rtl8168_mdio_write(tp, 0x1F, 0x0B82);
1124
+ uc_response = !!(rtl8168_mdio_read(tp, 0x10) & BIT_5);
1125
+ rtl8168_mdio_write(tp, 0x1F, 0x0B84);
1126
+ nctl_pc_range_fail = !!(rtl8168_mdio_read(tp, 0x11) & BIT_1);
1127
+ nctl_pc_stuck_fail = !!(rtl8168_mdio_read(tp, 0x11) & BIT_2);
1128
+ rtl8168_mdio_write(tp, 0x1F, 0x0000);
1129
+
1130
+ if (uc_response || nctl_pc_range_fail || nctl_pc_stuck_fail) {
1131
+ ResetPhyType = 3;
1132
+ } else {
1133
+ rtl8168_mdio_write(tp, 0x1F, 0x0C40);
1134
+ PhyRegValue = rtl8168_mdio_read(tp, 0x12);
1135
+ rtl8168_mdio_write(tp, 0x1F, 0x0000);
1136
+ if ((PhyRegValue & 0x03) != 0x00) {
1137
+ watch_dog = (u8)(PhyRegValue & 0x03);
1138
+ ResetPhyType = 2;
1139
+ }
1140
+ }
1141
+
1142
+ if (ResetPhyType == 0) goto exit;
1143
+
1144
+ netif_err(tp, drv, tp->dev, "test_phy_ocp ResetPhyType = 0x%02x\n.\n",
1145
+ ResetPhyType);
1146
1147
+ rtl8168_mdio_write(tp, 0x1F, 0x0C41);
1148
+ rtl8168_set_eth_phy_bit(tp, 0x14, BIT_0);
1149
+ rtl8168_mdio_write(tp, 0x1F, 0x0000);
1150
+ mdelay(24000); //24ms
1151
+
1152
+ rtl8168_mdio_write(tp, 0x1F, 0x0C40);
1153
+ PhyRegValue = rtl8168_mdio_read(tp, 0x12);
1154
+ if ((PhyRegValue & 0x03) != 0x00) {
1155
+ u32 WaitCnt = 0;
1156
+ while ((PhyRegValue & 0x03) != 0x00 && WaitCnt < 5) {
1157
+ rtl8168_mdio_write(tp, 0x1F, 0x0C40);
1158
+ rtl8168_set_eth_phy_bit(tp, 0x11, (BIT_15 | BIT_14));
1159
+ rtl8168_clear_eth_phy_bit(tp, 0x11, (BIT_15 | BIT_14));
1160
+ mdelay(100000);
1161
rtl8168_mdio_write(tp, 0x1F, 0x0C40);
1162
PhyRegValue = rtl8168_mdio_read(tp, 0x12);
1163
- if ((PhyRegValue & 0x03) != 0x00) {
1164
- WaitCnt = 0;
1165
- while ((PhyRegValue & 0x03) != 0x00 && WaitCnt < 5) {
1166
- rtl8168_mdio_write(tp, 0x1F, 0x0C40);
1167
- rtl8168_set_eth_phy_bit(tp, 0x11, (BIT_15 | BIT_14));
1168
- rtl8168_clear_eth_phy_bit(tp, 0x11, (BIT_15 | BIT_14));
1169
- mdelay(100);
1170
- rtl8168_mdio_write(tp, 0x1F, 0x0C40);
1171
- PhyRegValue = rtl8168_mdio_read(tp, 0x12);
1172
- WaitCnt++;
1173
- }
1174
- }
1175
+ WaitCnt++;
1176
+ }
1177
+ }
1178
1179
- rtl8168_mdio_write(tp, 0x1F, 0x0000);
1180
+ rtl8168_mdio_write(tp, 0x1F, 0x0000);
1181
1182
- rtl8168_mdio_write(tp, 0x1F, 0x0A46);
1183
- rtl8168_mdio_write(tp, 0x10, tp->BackupPhyFuseDout_15_0);
1184
- rtl8168_mdio_write(tp, 0x12, tp->BackupPhyFuseDout_47_32);
1185
- rtl8168_mdio_write(tp, 0x13, tp->BackupPhyFuseDout_63_48);
1186
- rtl8168_mdio_write(tp, 0x1F, 0x0000);
1187
+ //issue9
1188
+ rtl8168_mdio_write(tp, 0x1F, 0x0A46);
1189
+ rtl8168_mdio_write(tp, 0x10, tp->BackupPhyFuseDout_15_0);
1190
+ rtl8168_mdio_write(tp, 0x11, tp->BackupPhyFuseDout_31_16);
1191
+ rtl8168_mdio_write(tp, 0x12, tp->BackupPhyFuseDout_47_32);
1192
+ rtl8168_mdio_write(tp, 0x13, tp->BackupPhyFuseDout_63_48);
1193
+ rtl8168_mdio_write(tp, 0x1F, 0x0000);
1194
1195
- rtl8168_wait_phy_state_ready(tp, HW_PHY_STATUS_INI, 5000000);
1196
- rtl8168_mdio_write(tp, 0x1F, 0x0A46);
1197
- rtl8168_set_eth_phy_bit(tp, 0x14, BIT_0);
1198
- rtl8168_mdio_write(tp, 0x1F, 0x0000);
1199
- rtl8168_wait_phy_state_ready(tp, HW_PHY_STATUS_LAN_ON, 500000);
1200
+ rtl8168_wait_phy_state_ready(tp, HW_PHY_STATUS_INI, 5000000);
1201
+ rtl8168_mdio_write(tp, 0x1F, 0x0A46);
1202
+ rtl8168_set_eth_phy_bit(tp, 0x14, BIT_0);
1203
+ rtl8168_mdio_write(tp, 0x1F, 0x0000);
1204
+ rtl8168_wait_phy_state_ready(tp, HW_PHY_STATUS_LAN_ON, 500000);
1205
1206
- tp->HwHasWrRamCodeToMicroP = FALSE;
1207
+ //record fail case
1208
+ rtl8168_mdio_write(tp, 0x1F, 0x0A43);
1209
+ rtl8168_mdio_write(tp, 0x13, 0x801C);
1210
+ PhyRegValue = 0;
1211
+ PhyRegValue = watch_dog & 0x03;
1212
+ PhyRegValue <<= 14;
1213
+ if (uc_response) PhyRegValue |= BIT_13;
1214
+ if (nctl_pc_range_fail) PhyRegValue |= BIT_12;
1215
+ if (nctl_pc_stuck_fail) PhyRegValue |= BIT_11;
1216
+ ClearAndSetEthPhyBit(tp,
1217
+ 0x14,
1218
+ 0xF800,
1219
+ PhyRegValue);
1220
+ rtl8168_mdio_write(tp, 0x1F, 0x0000);
1221
1222
- RestorePhyOcpReg = TRUE;
1223
- }
1224
+ tp->HwHasWrRamCodeToMicroP = FALSE;
1225
1226
- rtl8168_mdio_write(tp, 0x1F, 0x0000);
1227
+ RestorePhyOcpReg = TRUE;
1228
+
1229
+exit:
1230
+ //set uc_response to 1 and gphy should auto clear it.
1231
+ rtl8168_mdio_write(tp, 0x1F, 0x0B82);
1232
+ rtl8168_set_eth_phy_bit(tp, 0x10, BIT_5);
1233
+ rtl8168_mdio_write(tp, 0x1F, 0x0000);
1234
+
1235
+ return RestorePhyOcpReg;
1236
+}
1237
+
1238
+static
1239
+bool
1240
+rtl8168_test_phy_ocp(struct rtl8168_private *tp)
1241
+{
1242
+ bool RestorePhyOcpReg = FALSE;
1243
+
1244
+ if (tp->TestPhyOcpReg == FALSE) goto exit;
1245
+
1246
+ switch (tp->HwSuppEsdVer) {
1247
+ case 2:
1248
+ RestorePhyOcpReg = rtl8168_test_phy_ocp_v2(tp);
1249
+ break;
1250
+ case 3:
1251
+ RestorePhyOcpReg = rtl8168_test_phy_ocp_v3(tp);
1252
+ break;
1253
+ default:
1254
+ break;
1255
}
1256
1257
exit:
1258
1259
case CFG_METHOD_31:
1260
case CFG_METHOD_32:
1261
case CFG_METHOD_33:
1262
+ case CFG_METHOD_34:
1263
rtl8168_eri_write(tp, 0x174, 2, 0x00FF, ERIAR_ExGMAC);
1264
rtl8168_mac_ocp_write(tp, 0xE428, 0x0010);
1265
break;
1266
case CFG_METHOD_29:
1267
- case CFG_METHOD_30: {
1268
+ case CFG_METHOD_30:
1269
+ case CFG_METHOD_35: {
1270
u32 csi_tmp;
1271
csi_tmp = rtl8168_eri_read(tp, 0x174, 2, ERIAR_ExGMAC);
1272
csi_tmp &= ~(BIT_8);
1273
1274
case CFG_METHOD_31:
1275
case CFG_METHOD_32:
1276
case CFG_METHOD_33:
1277
+ case CFG_METHOD_34:
1278
+ case CFG_METHOD_35:
1279
rtl8168_disable_now_is_oob(tp);
1280
1281
data16 = rtl8168_mac_ocp_read(tp, 0xE8DE) & ~BIT_14;
1282
1283
1284
#ifdef ENABLE_FIBER_SUPPORT
1285
if (HW_FIBER_MODE_ENABLED(tp))
1286
- rtl8168_hw_init_fiber_nic(dev);
1287
+ rtl8168_hw_init_fiber_nic(tp);
1288
#endif //ENABLE_FIBER_SUPPORT
1289
}
1290
1291
1292
case CFG_METHOD_31:
1293
case CFG_METHOD_32:
1294
case CFG_METHOD_33:
1295
+ case CFG_METHOD_34:
1296
+ case CFG_METHOD_35:
1297
rtl8168_mac_ocp_write(tp, 0xFC38, 0x0000);
1298
break;
1299
}
1300
1301
case CFG_METHOD_31:
1302
case CFG_METHOD_32:
1303
case CFG_METHOD_33:
1304
+ case CFG_METHOD_34:
1305
+ case CFG_METHOD_35:
1306
rtl8168_mac_ocp_write(tp, 0xFC28, 0x0000);
1307
rtl8168_mac_ocp_write(tp, 0xFC2A, 0x0000);
1308
rtl8168_mac_ocp_write(tp, 0xFC2C, 0x0000);
1309
1310
rtl8168_mac_ocp_write(tp, 0xFC2C, 0x0763);
1311
}
1312
1313
+static bool
1314
+rtl8168_check_dash_other_fun_present(struct rtl8168_private *tp)
1315
+{
1316
+ //check if func 2 exist
1317
+ if (rtl8168_csi_other_fun_read(tp, 2, 0x00) != 0xffffffff)
1318
+ return true;
1319
+
1320
+ return false;
1321
+}
1322
+
1323
static void
1324
rtl8168_set_mac_mcu_8168ep_2(struct net_device *dev)
1325
{
1326
struct rtl8168_private *tp = netdev_priv(dev);
1327
u16 i;
1328
static const u16 mcu_patch_code_8168ep_2 = {
1329
- 0xE008, 0xE017, 0xE052, 0xE056, 0xE058, 0xE05A, 0xE05C, 0xE05E, 0xC50F,
1330
+ 0xE008, 0xE017, 0xE052, 0xE057, 0xE059, 0xE05B, 0xE05D, 0xE05F, 0xC50F,
1331
0x76A4, 0x49E3, 0xF007, 0x49C0, 0xF103, 0xC607, 0xBE00, 0xC606, 0xBE00,
1332
0xC602, 0xBE00, 0x0BDA, 0x0BB6, 0x0BBA, 0xDC00, 0xB400, 0xB401, 0xB402,
1333
0xB403, 0xB404, 0xC02E, 0x7206, 0x49AE, 0xF1FE, 0xC12B, 0x9904, 0xC12A,
1334
1335
0x740E, 0x49CE, 0xF1FE, 0x9908, 0x990A, 0x9A0C, 0x9B0E, 0x740E, 0x49CE,
1336
0xF1FE, 0xFF80, 0xB004, 0xB003, 0xB002, 0xB001, 0xB000, 0xC604, 0xC002,
1337
0xB800, 0x1FC8, 0xE000, 0xE8E0, 0xF128, 0x0002, 0xFFFF, 0xF000, 0x8001,
1338
- 0x8002, 0x8003, 0x8004, 0x48C1, 0x48C2, 0xC502, 0xBD00, 0x0490, 0xC602,
1339
- 0xBE00, 0x0000, 0xC602, 0xBE00, 0x0000, 0xC602, 0xBE00, 0x0000, 0xC602,
1340
- 0xBE00, 0x0000, 0xC602, 0xBE00, 0x0000,
1341
+ 0x8002, 0x8003, 0x8004, 0x48C1, 0x48C2, 0x9C46, 0xC402, 0xBC00, 0x0490,
1342
+ 0xC602, 0xBE00, 0x0000, 0xC602, 0xBE00, 0x0000, 0xC602, 0xBE00, 0x0000,
1343
+ 0xC602, 0xBE00, 0x0000, 0xC602, 0xBE00, 0x0000
1344
};
1345
1346
rtl8168_hw_disable_mac_mcu_bps(dev);
1347
1348
rtl8168_mac_ocp_write(tp, 0xFC26, 0x8000);
1349
1350
rtl8168_mac_ocp_write(tp, 0xFC28, 0x0BB3);
1351
- rtl8168_mac_ocp_write(tp, 0xFC2A, 0x1FC7);
1352
- rtl8168_mac_ocp_write(tp, 0xFC2C, 0x0485);
1353
+ if (false == rtl8168_check_dash_other_fun_present(tp))
1354
+ rtl8168_mac_ocp_write(tp, 0xFC2A, 0x1FC7);
1355
+ //rtl8168_mac_ocp_write(tp, 0xFC2C, 0x0485);
1356
}
1357
1358
static void
1359
rtl8168_set_mac_mcu_8168h_1(struct net_device *dev)
1360
{
1361
+ rtl8168_hw_disable_mac_mcu_bps(dev);
1362
+}
1363
+
1364
+static void
1365
+rtl8168_set_mac_mcu_8168h_2(struct net_device *dev)
1366
+{
1367
struct rtl8168_private *tp = netdev_priv(dev);
1368
u16 i;
1369
static const u16 mcu_patch_code_8168h_1 = {
1370
- 0xE008, 0xE00F, 0xE011, 0xE047, 0xE049, 0xE073, 0xE075, 0xE079, 0xC707,
1371
+ 0xE008, 0xE00F, 0xE011, 0xE047, 0xE049, 0xE073, 0xE075, 0xE07A, 0xC707,
1372
0x1D00, 0x8DE2, 0x48C1, 0xC502, 0xBD00, 0x00E4, 0xE0C0, 0xC502, 0xBD00,
1373
0x0216, 0xC634, 0x75C0, 0x49D3, 0xF027, 0xC631, 0x75C0, 0x49D3, 0xF123,
1374
0xC627, 0x75C0, 0xB405, 0xC525, 0x9DC0, 0xC621, 0x75C8, 0x49D5, 0xF00A,
1375
1376
0xC71C, 0xC419, 0x9CE0, 0x1C13, 0x484F, 0x9CE2, 0x74E2, 0x49CE, 0xF1FE,
1377
0xC412, 0x9CE0, 0x1C13, 0x484F, 0x9CE2, 0x74E2, 0x49CE, 0xF1FE, 0xC70C,
1378
0x74F8, 0x48C3, 0x8CF8, 0xB004, 0xB007, 0xC502, 0xBD00, 0x0F24, 0x0481,
1379
- 0x0C81, 0xDE24, 0xE000, 0xC602, 0xBE00, 0x0CA4, 0x48C1, 0x48C2, 0xC502,
1380
- 0xBD00, 0x0578, 0xC602, 0xBE00, 0x0000
1381
+ 0x0C81, 0xDE24, 0xE000, 0xC602, 0xBE00, 0x0CA4, 0x48C1, 0x48C2, 0x9C46,
1382
+ 0xC402, 0xBC00, 0x0578, 0xC602, 0xBE00, 0x0000
1383
};
1384
1385
rtl8168_hw_disable_mac_mcu_bps(dev);
1386
1387
rtl8168_mac_ocp_write(tp, 0xFC2E, 0x0B26);
1388
rtl8168_mac_ocp_write(tp, 0xFC30, 0x0F02);
1389
rtl8168_mac_ocp_write(tp, 0xFC32, 0x0CA0);
1390
- rtl8168_mac_ocp_write(tp, 0xFC34, 0x056C);
1391
+ //rtl8168_mac_ocp_write(tp, 0xFC34, 0x056C);
1392
+
1393
+ rtl8168_mac_ocp_write(tp, 0xFC38, 0x003F);
1394
+}
1395
1396
- rtl8168_mac_ocp_write(tp, 0xFC38, 0x007F);
1397
+static void
1398
+rtl8168_set_mac_mcu_8168h_3(struct net_device *dev)
1399
+{
1400
+ rtl8168_hw_disable_mac_mcu_bps(dev);
1401
}
1402
1403
static void
1404
1405
}
1406
1407
static void
1408
-rtl8168_set_mac_mcu_8168fp_2(struct net_device *dev)
1409
+rtl8168_set_mac_mcu_8168fp_8116as_2(struct net_device *dev)
1410
{
1411
struct rtl8168_private *tp = netdev_priv(dev);
1412
u16 i;
1413
- static const u16 mcu_patch_code_8168fp_2 = {
1414
- 0xE008, 0xE00A, 0xE00F, 0xE014, 0xE05F, 0xE063, 0xE065, 0xE067, 0xC602,
1415
+ static const u16 mcu_patch_code_8168fp_8116as_2 = {
1416
+ 0xE008, 0xE00A, 0xE00F, 0xE014, 0xE016, 0xE018, 0xE01A, 0xE01C, 0xC602,
1417
0xBE00, 0x2AB2, 0x1BC0, 0x46EB, 0x1BFE, 0xC102, 0xB900, 0x0B1A, 0x1BC0,
1418
+ 0x46EB, 0x1B7E, 0xC102, 0xB900, 0x0BEA, 0xC602, 0xBE00, 0x0000, 0xC602,
1419
+ 0xBE00, 0x0000, 0xC602, 0xBE00, 0x0000, 0xC602, 0xBE00, 0x0000, 0xC602,
1420
+ 0xBE00, 0x0000
1421
+ };
1422
+
1423
+ rtl8168_hw_disable_mac_mcu_bps(dev);
1424
+
1425
+ for (i = 0; i < ARRAY_SIZE(mcu_patch_code_8168fp_8116as_2); i++) {
1426
+ rtl8168_mac_ocp_write(tp, 0xF800 + i * 2, mcu_patch_code_8168fp_8116as_2i);
1427
+ }
1428
+
1429
+ rtl8168_mac_ocp_write(tp, 0xFC26, 0x8000);
1430
+
1431
+ rtl8168_mac_ocp_write(tp, 0xFC28, 0x2AAC);
1432
+ rtl8168_mac_ocp_write(tp, 0xFC2A, 0x0B14);
1433
+ rtl8168_mac_ocp_write(tp, 0xFC2C, 0x0BE4);
1434
+
1435
+ rtl8168_mac_ocp_write(tp, 0xFC38, 0x0007);
1436
+}
1437
+
1438
+static void
1439
+_rtl8168_set_mac_mcu_8168fp_2(struct net_device *dev)
1440
+{
1441
+ struct rtl8168_private *tp = netdev_priv(dev);
1442
+ u16 i;
1443
+ static const u16 mcu_patch_code_8168fp_2 = {
1444
+ 0xE008, 0xE00A, 0xE00F, 0xE014, 0xE05F, 0xE064, 0xE066, 0xE068, 0xC602,
1445
+ 0xBE00, 0x0000, 0x1BC0, 0x46EB, 0x1BFE, 0xC102, 0xB900, 0x0B1A, 0x1BC0,
1446
0x46EB, 0x1B7E, 0xC102, 0xB900, 0x0BEA, 0xB400, 0xB401, 0xB402, 0xB403,
1447
0xB404, 0xB405, 0xC03A, 0x7206, 0x49AE, 0xF1FE, 0xC137, 0x9904, 0xC136,
1448
0x9906, 0x7206, 0x49AE, 0xF1FE, 0x7200, 0x49A0, 0xF10B, 0xC52F, 0xC12E,
1449
1450
0x740E, 0x49CE, 0xF1FE, 0xFF80, 0xB005, 0xB004, 0xB003, 0xB002, 0xB001,
1451
0xB000, 0xC604, 0xC002, 0xB800, 0x2A5E, 0xE000, 0xE8E0, 0xF128, 0x3DC2,
1452
0xFFFF, 0x10EC, 0x816A, 0x816D, 0x816C, 0xF000, 0x8002, 0x8004, 0x8007,
1453
- 0x48C1, 0x48C2, 0xC502, 0xBD00, 0x07BC, 0xC602, 0xBE00, 0x0000, 0xC602,
1454
- 0xBE00, 0x0000, 0xC602, 0xBE00, 0x0000
1455
+ 0x48C1, 0x48C2, 0x9C46, 0xC402, 0xBC00, 0x07BC, 0xC602, 0xBE00, 0x0000,
1456
+ 0xC602, 0xBE00, 0x0000, 0xC602, 0xBE00, 0x0000
1457
};
1458
1459
rtl8168_hw_disable_mac_mcu_bps(dev);
1460
1461
rtl8168_mac_ocp_write(tp, 0xFC2A, 0x0B14);
1462
rtl8168_mac_ocp_write(tp, 0xFC2C, 0x0BE4);
1463
rtl8168_mac_ocp_write(tp, 0xFC2E, 0x2A5C);
1464
- rtl8168_mac_ocp_write(tp, 0xFC30, 0x07B0);
1465
+ //rtl8168_mac_ocp_write(tp, 0xFC30, 0x07B0);
1466
1467
- if (tp->HwSuppSerDesPhyVer == 1)
1468
- rtl8168_mac_ocp_write(tp, 0xFC38, 0x001F);
1469
+ if (true == rtl8168_check_dash_other_fun_present(tp))
1470
+ rtl8168_mac_ocp_write(tp, 0xFC38, 0x0006);
1471
else
1472
- rtl8168_mac_ocp_write(tp, 0xFC38, 0x001E);
1473
+ rtl8168_mac_ocp_write(tp, 0xFC38, 0x000E);
1474
+}
1475
1476
+static void
1477
+rtl8168_set_mac_mcu_8168fp_2(struct net_device *dev)
1478
+{
1479
+ struct rtl8168_private *tp = netdev_priv(dev);
1480
+
1481
+ if (tp->HwSuppSerDesPhyVer == 1) rtl8168_set_mac_mcu_8168fp_8116as_2(dev);
1482
+ else _rtl8168_set_mac_mcu_8168fp_2(dev);
1483
}
1484
1485
static void
1486
1487
struct rtl8168_private *tp = netdev_priv(dev);
1488
u16 i;
1489
static const u16 mcu_patch_code_8168fp_3 = {
1490
- 0xE008, 0xE053, 0xE057, 0xE059, 0xE05B, 0xE05D, 0xE05F, 0xE061, 0xB400,
1491
+ 0xE008, 0xE053, 0xE058, 0xE05A, 0xE05C, 0xE05E, 0xE060, 0xE062, 0xB400,
1492
0xB401, 0xB402, 0xB403, 0xB404, 0xB405, 0xC03A, 0x7206, 0x49AE, 0xF1FE,
1493
0xC137, 0x9904, 0xC136, 0x9906, 0x7206, 0x49AE, 0xF1FE, 0x7200, 0x49A0,
1494
0xF10B, 0xC52F, 0xC12E, 0xC232, 0xC332, 0xE812, 0xC331, 0xE810, 0xC330,
1495
1496
0x9D0A, 0x9A0C, 0x9B0E, 0x740E, 0x49CE, 0xF1FE, 0xFF80, 0xB005, 0xB004,
1497
0xB003, 0xB002, 0xB001, 0xB000, 0xC604, 0xC002, 0xB800, 0x2B16, 0xE000,
1498
0xE8E0, 0xF128, 0x3DC2, 0xFFFF, 0x10EC, 0x816A, 0x816D, 0x816C, 0xF000,
1499
- 0x8002, 0x8004, 0x8007, 0x48C1, 0x48C2, 0xC502, 0xBD00, 0x07BC, 0xC602,
1500
- 0xBE00, 0x0000, 0xC602, 0xBE00, 0x0000, 0xC602, 0xBE00, 0x0000, 0xC602,
1501
- 0xBE00, 0x0000, 0xC602, 0xBE00, 0x0000, 0xC602, 0xBE00, 0x0000
1502
+ 0x8002, 0x8004, 0x8007, 0x48C1, 0x48C2, 0x9C46, 0xC402, 0xBC00, 0x07BC,
1503
+ 0xC602, 0xBE00, 0x0000, 0xC602, 0xBE00, 0x0000, 0xC602, 0xBE00, 0x0000,
1504
+ 0xC602, 0xBE00, 0x0000, 0xC602, 0xBE00, 0x0000, 0xC602, 0xBE00, 0x0000
1505
};
1506
1507
rtl8168_hw_disable_mac_mcu_bps(dev);
1508
1509
rtl8168_mac_ocp_write(tp, 0xFC26, 0x8000);
1510
1511
rtl8168_mac_ocp_write(tp, 0xFC28, 0x2B14);
1512
- rtl8168_mac_ocp_write(tp, 0xFC2A, 0x07B0);
1513
+ //rtl8168_mac_ocp_write(tp, 0xFC2A, 0x07B0);
1514
1515
- rtl8168_mac_ocp_write(tp, 0xFC38, 0x0003);
1516
+ if (true == rtl8168_check_dash_other_fun_present(tp))
1517
+ rtl8168_mac_ocp_write(tp, 0xFC38, 0x0000);
1518
+ else
1519
+ rtl8168_mac_ocp_write(tp, 0xFC38, 0x0001);
1520
}
1521
1522
static void
1523
1524
rtl8168_set_mac_mcu_8168ep_2(dev);
1525
break;
1526
case CFG_METHOD_29:
1527
- case CFG_METHOD_30:
1528
rtl8168_set_mac_mcu_8168h_1(dev);
1529
break;
1530
+ case CFG_METHOD_30:
1531
+ rtl8168_set_mac_mcu_8168h_2(dev);
1532
+ break;
1533
case CFG_METHOD_31:
1534
rtl8168_set_mac_mcu_8168fp_1(dev);
1535
break;
1536
1537
rtl8168_set_mac_mcu_8168fp_2(dev);
1538
break;
1539
case CFG_METHOD_33:
1540
+ case CFG_METHOD_34:
1541
rtl8168_set_mac_mcu_8168fp_3(dev);
1542
break;
1543
+ case CFG_METHOD_35:
1544
+ rtl8168_set_mac_mcu_8168h_3(dev);
1545
+ break;
1546
}
1547
}
1548
#endif
1549
1550
case CFG_METHOD_31:
1551
case CFG_METHOD_32:
1552
case CFG_METHOD_33:
1553
+ case CFG_METHOD_34:
1554
+ case CFG_METHOD_35:
1555
rtl8168_mac_ocp_write(tp, 0xE63E, rtl8168_mac_ocp_read( tp, 0xE63E) & ~(BIT_3 | BIT_2 | BIT_1));
1556
rtl8168_mac_ocp_write(tp, 0xE63E, rtl8168_mac_ocp_read( tp, 0xE63E) | (BIT_0));
1557
rtl8168_mac_ocp_write(tp, 0xE63E, rtl8168_mac_ocp_read( tp, 0xE63E) & ~(BIT_0));
1558
1559
case CFG_METHOD_22:
1560
case CFG_METHOD_29:
1561
case CFG_METHOD_30:
1562
+ case CFG_METHOD_35:
1563
if (aspm) {
1564
if ((rtl8168_mac_ocp_read(tp, 0xDC00) & BIT_3) || (RTL_R8(tp, Config0) & 0x07)) {
1565
RTL_W8(tp, 0x6E, RTL_R8(tp, 0x6E) | BIT_6);
1566
1567
tp->mcfg == CFG_METHOD_27 || tp->mcfg == CFG_METHOD_28 ||
1568
tp->mcfg == CFG_METHOD_29 || tp->mcfg == CFG_METHOD_30 ||
1569
tp->mcfg == CFG_METHOD_31 || tp->mcfg == CFG_METHOD_32 ||
1570
- tp->mcfg == CFG_METHOD_33)
1571
+ tp->mcfg == CFG_METHOD_33 || tp->mcfg == CFG_METHOD_34 ||
1572
+ tp->mcfg == CFG_METHOD_35)
1573
if (!tp->dash_printer_enabled)
1574
rtl8168_disable_ocp_phy_power_saving(dev);
1575
1576
1577
case CFG_METHOD_31:
1578
case CFG_METHOD_32:
1579
case CFG_METHOD_33:
1580
+ case CFG_METHOD_34:
1581
ClearAndSetPCIePhyBit(tp,
1582
0x19,
1583
BIT_6,
1584
1585
ClearPCIePhyBit(tp, 0x0B, BIT_0);
1586
1587
break;
1588
+ case CFG_METHOD_35:
1589
+ rtl8168_clear_mcu_ocp_bit(tp, 0xDE28, (BIT_1 | BIT_0));
1590
+
1591
+ rtl8168_set_mcu_ocp_bit(tp, 0xDE38, (BIT_2));
1592
+
1593
+ break;
1594
}
1595
}
1596
1597
1598
int retval = TRUE;
1599
1600
switch (tp->mcfg) {
1601
- case CFG_METHOD_21 ... CFG_METHOD_33:
1602
+ case CFG_METHOD_21 ... CFG_METHOD_34:
1603
rtl8168_mdio_write(tp,0x1f, 0x0B82);
1604
rtl8168_set_eth_phy_bit(tp, 0x10, BIT_4);
1605
1606
1607
int retval = TRUE;
1608
1609
switch (tp->mcfg) {
1610
- case CFG_METHOD_21 ... CFG_METHOD_33:
1611
+ case CFG_METHOD_21 ... CFG_METHOD_34:
1612
rtl8168_mdio_write(tp, 0x1f, 0x0B82);
1613
rtl8168_clear_eth_phy_bit(tp, 0x10, BIT_4);
1614
1615
1616
case CFG_METHOD_31:
1617
case CFG_METHOD_32:
1618
case CFG_METHOD_33:
1619
+ case CFG_METHOD_34:
1620
+ case CFG_METHOD_35:
1621
rtl8168_mdio_write(tp, 0x1F, 0x0A43);
1622
rtl8168_mdio_write(tp, 0x13, 0x801E);
1623
hw_ram_code_ver = rtl8168_mdio_read(tp, 0x14);
1624
1625
case CFG_METHOD_31:
1626
case CFG_METHOD_32:
1627
case CFG_METHOD_33:
1628
+ case CFG_METHOD_34:
1629
+ case CFG_METHOD_35:
1630
rtl8168_mdio_write(tp, 0x1F, 0x0A43);
1631
rtl8168_mdio_write(tp, 0x13, 0x801E);
1632
rtl8168_mdio_write(tp, 0x14, tp->sw_ram_code_ver);
1633
1634
}
1635
1636
static void
1637
+rtl8168_set_phy_mcu_8168h_3(struct net_device *dev)
1638
+{
1639
+ struct rtl8168_private *tp = netdev_priv(dev);
1640
+ unsigned int gphy_val;
1641
+
1642
+ rtl8168_set_phy_mcu_patch_request(tp);
1643
+
1644
+ rtl8168_mdio_write(tp, 0x1f, 0x0A43);
1645
+ rtl8168_mdio_write(tp, 0x13, 0x8042);
1646
+ rtl8168_mdio_write(tp, 0x14, 0x3800);
1647
+ rtl8168_mdio_write(tp, 0x13, 0xB82E);
1648
+ rtl8168_mdio_write(tp, 0x14, 0x0001);
1649
+
1650
+
1651
+ rtl8168_mdio_write(tp, 0x1F, 0x0A43);
1652
+ rtl8168_mdio_write(tp, 0x13, 0xB820);
1653
+ rtl8168_mdio_write(tp, 0x14, 0x0090);
1654
+ rtl8168_mdio_write(tp, 0x13, 0xA016);
1655
+ rtl8168_mdio_write(tp, 0x14, 0x0000);
1656
+ rtl8168_mdio_write(tp, 0x13, 0xA012);
1657
+ rtl8168_mdio_write(tp, 0x14, 0x0000);
1658
+ rtl8168_mdio_write(tp, 0x13, 0xA014);
1659
+ rtl8168_mdio_write(tp, 0x14, 0x1800);
1660
+ rtl8168_mdio_write(tp, 0x14, 0x8002);
1661
+ rtl8168_mdio_write(tp, 0x14, 0x2b5d);
1662
+ rtl8168_mdio_write(tp, 0x14, 0x0c68);
1663
+ rtl8168_mdio_write(tp, 0x14, 0x1800);
1664
+ rtl8168_mdio_write(tp, 0x14, 0x0b3c);
1665
+ rtl8168_mdio_write(tp, 0x13, 0xA000);
1666
+ rtl8168_mdio_write(tp, 0x14, 0x0b3a);
1667
+ rtl8168_mdio_write(tp, 0x13, 0xA008);
1668
+ rtl8168_mdio_write(tp, 0x14, 0x0100);
1669
+ rtl8168_mdio_write(tp, 0x13, 0xB820);
1670
+ rtl8168_mdio_write(tp, 0x14, 0x0010);
1671
+
1672
+
1673
+ rtl8168_mdio_write(tp, 0x13, 0x83f3);
1674
+ rtl8168_mdio_write(tp, 0x14, 0xaf84);
1675
+ rtl8168_mdio_write(tp, 0x14, 0x0baf);
1676
+ rtl8168_mdio_write(tp, 0x14, 0x8466);
1677
+ rtl8168_mdio_write(tp, 0x14, 0xaf84);
1678
+ rtl8168_mdio_write(tp, 0x14, 0xcdaf);
1679
+ rtl8168_mdio_write(tp, 0x14, 0x8736);
1680
+ rtl8168_mdio_write(tp, 0x14, 0xaf87);
1681
+ rtl8168_mdio_write(tp, 0x14, 0x39af);
1682
+ rtl8168_mdio_write(tp, 0x14, 0x8739);
1683
+ rtl8168_mdio_write(tp, 0x14, 0xaf87);
1684
+ rtl8168_mdio_write(tp, 0x14, 0x39af);
1685
+ rtl8168_mdio_write(tp, 0x14, 0x8739);
1686
+ rtl8168_mdio_write(tp, 0x14, 0xef79);
1687
+ rtl8168_mdio_write(tp, 0x14, 0xfb89);
1688
+ rtl8168_mdio_write(tp, 0x14, 0xe987);
1689
+ rtl8168_mdio_write(tp, 0x14, 0xffd7);
1690
+ rtl8168_mdio_write(tp, 0x14, 0x0017);
1691
+ rtl8168_mdio_write(tp, 0x14, 0xd400);
1692
+ rtl8168_mdio_write(tp, 0x14, 0x051c);
1693
+ rtl8168_mdio_write(tp, 0x14, 0x421a);
1694
+ rtl8168_mdio_write(tp, 0x14, 0x741b);
1695
+ rtl8168_mdio_write(tp, 0x14, 0x97e9);
1696
+ rtl8168_mdio_write(tp, 0x14, 0x87fe);
1697
+ rtl8168_mdio_write(tp, 0x14, 0xffef);
1698
+ rtl8168_mdio_write(tp, 0x14, 0x97e0);
1699
+ rtl8168_mdio_write(tp, 0x14, 0x82aa);
1700
+ rtl8168_mdio_write(tp, 0x14, 0xa000);
1701
+ rtl8168_mdio_write(tp, 0x14, 0x08ef);
1702
+ rtl8168_mdio_write(tp, 0x14, 0x46dc);
1703
+ rtl8168_mdio_write(tp, 0x14, 0x19dd);
1704
+ rtl8168_mdio_write(tp, 0x14, 0xaf1a);
1705
+ rtl8168_mdio_write(tp, 0x14, 0x37a0);
1706
+ rtl8168_mdio_write(tp, 0x14, 0x012d);
1707
+ rtl8168_mdio_write(tp, 0x14, 0xe082);
1708
+ rtl8168_mdio_write(tp, 0x14, 0xa7ac);
1709
+ rtl8168_mdio_write(tp, 0x14, 0x2013);
1710
+ rtl8168_mdio_write(tp, 0x14, 0xe087);
1711
+ rtl8168_mdio_write(tp, 0x14, 0xffe1);
1712
+ rtl8168_mdio_write(tp, 0x14, 0x87fe);
1713
+ rtl8168_mdio_write(tp, 0x14, 0xac27);
1714
+ rtl8168_mdio_write(tp, 0x14, 0x05a1);
1715
+ rtl8168_mdio_write(tp, 0x14, 0x0807);
1716
+ rtl8168_mdio_write(tp, 0x14, 0xae0f);
1717
+ rtl8168_mdio_write(tp, 0x14, 0xa107);
1718
+ rtl8168_mdio_write(tp, 0x14, 0x02ae);
1719
+ rtl8168_mdio_write(tp, 0x14, 0x0aef);
1720
+ rtl8168_mdio_write(tp, 0x14, 0x4619);
1721
+ rtl8168_mdio_write(tp, 0x14, 0x19dc);
1722
+ rtl8168_mdio_write(tp, 0x14, 0x19dd);
1723
+ rtl8168_mdio_write(tp, 0x14, 0xaf1a);
1724
+ rtl8168_mdio_write(tp, 0x14, 0x37d8);
1725
+ rtl8168_mdio_write(tp, 0x14, 0x19d9);
1726
+ rtl8168_mdio_write(tp, 0x14, 0x19dc);
1727
+ rtl8168_mdio_write(tp, 0x14, 0x19dd);
1728
+ rtl8168_mdio_write(tp, 0x14, 0xaf1a);
1729
+ rtl8168_mdio_write(tp, 0x14, 0x3719);
1730
+ rtl8168_mdio_write(tp, 0x14, 0x19ae);
1731
+ rtl8168_mdio_write(tp, 0x14, 0xcfbf);
1732
+ rtl8168_mdio_write(tp, 0x14, 0x8763);
1733
+ rtl8168_mdio_write(tp, 0x14, 0x0244);
1734
+ rtl8168_mdio_write(tp, 0x14, 0xdc3c);
1735
+ rtl8168_mdio_write(tp, 0x14, 0x0005);
1736
+ rtl8168_mdio_write(tp, 0x14, 0xaaf5);
1737
+ rtl8168_mdio_write(tp, 0x14, 0x0249);
1738
+ rtl8168_mdio_write(tp, 0x14, 0xcaef);
1739
+ rtl8168_mdio_write(tp, 0x14, 0x67d7);
1740
+ rtl8168_mdio_write(tp, 0x14, 0x0014);
1741
+ rtl8168_mdio_write(tp, 0x14, 0x0249);
1742
+ rtl8168_mdio_write(tp, 0x14, 0xe5ad);
1743
+ rtl8168_mdio_write(tp, 0x14, 0x50f7);
1744
+ rtl8168_mdio_write(tp, 0x14, 0xd400);
1745
+ rtl8168_mdio_write(tp, 0x14, 0x01bf);
1746
+ rtl8168_mdio_write(tp, 0x14, 0x46a7);
1747
+ rtl8168_mdio_write(tp, 0x14, 0x0244);
1748
+ rtl8168_mdio_write(tp, 0x14, 0x98bf);
1749
+ rtl8168_mdio_write(tp, 0x14, 0x465c);
1750
+ rtl8168_mdio_write(tp, 0x14, 0x024a);
1751
+ rtl8168_mdio_write(tp, 0x14, 0x5fd4);
1752
+ rtl8168_mdio_write(tp, 0x14, 0x0003);
1753
+ rtl8168_mdio_write(tp, 0x14, 0xbf87);
1754
+ rtl8168_mdio_write(tp, 0x14, 0x7502);
1755
+ rtl8168_mdio_write(tp, 0x14, 0x4498);
1756
+ rtl8168_mdio_write(tp, 0x14, 0xbf87);
1757
+ rtl8168_mdio_write(tp, 0x14, 0x7202);
1758
+ rtl8168_mdio_write(tp, 0x14, 0x4a5f);
1759
+ rtl8168_mdio_write(tp, 0x14, 0xbf87);
1760
+ rtl8168_mdio_write(tp, 0x14, 0x6602);
1761
+ rtl8168_mdio_write(tp, 0x14, 0x4a5f);
1762
+ rtl8168_mdio_write(tp, 0x14, 0xbf87);
1763
+ rtl8168_mdio_write(tp, 0x14, 0x6902);
1764
+ rtl8168_mdio_write(tp, 0x14, 0x44dc);
1765
+ rtl8168_mdio_write(tp, 0x14, 0xad28);
1766
+ rtl8168_mdio_write(tp, 0x14, 0xf7bf);
1767
+ rtl8168_mdio_write(tp, 0x14, 0x876f);
1768
+ rtl8168_mdio_write(tp, 0x14, 0x0244);
1769
+ rtl8168_mdio_write(tp, 0x14, 0xdcad);
1770
+ rtl8168_mdio_write(tp, 0x14, 0x28f7);
1771
+ rtl8168_mdio_write(tp, 0x14, 0xbf87);
1772
+ rtl8168_mdio_write(tp, 0x14, 0x6c02);
1773
+ rtl8168_mdio_write(tp, 0x14, 0x4a5f);
1774
+ rtl8168_mdio_write(tp, 0x14, 0xbf87);
1775
+ rtl8168_mdio_write(tp, 0x14, 0x6c02);
1776
+ rtl8168_mdio_write(tp, 0x14, 0x4a56);
1777
+ rtl8168_mdio_write(tp, 0x14, 0xbf46);
1778
+ rtl8168_mdio_write(tp, 0x14, 0x5c02);
1779
+ rtl8168_mdio_write(tp, 0x14, 0x4a56);
1780
+ rtl8168_mdio_write(tp, 0x14, 0xbf45);
1781
+ rtl8168_mdio_write(tp, 0x14, 0x21af);
1782
+ rtl8168_mdio_write(tp, 0x14, 0x020e);
1783
+ rtl8168_mdio_write(tp, 0x14, 0xee82);
1784
+ rtl8168_mdio_write(tp, 0x14, 0x5000);
1785
+ rtl8168_mdio_write(tp, 0x14, 0x0284);
1786
+ rtl8168_mdio_write(tp, 0x14, 0xdd02);
1787
+ rtl8168_mdio_write(tp, 0x14, 0x8521);
1788
+ rtl8168_mdio_write(tp, 0x14, 0x0285);
1789
+ rtl8168_mdio_write(tp, 0x14, 0x36af);
1790
+ rtl8168_mdio_write(tp, 0x14, 0x03d2);
1791
+ rtl8168_mdio_write(tp, 0x14, 0xf8f9);
1792
+ rtl8168_mdio_write(tp, 0x14, 0xfafb);
1793
+ rtl8168_mdio_write(tp, 0x14, 0xef59);
1794
+ rtl8168_mdio_write(tp, 0x14, 0xbf45);
1795
+ rtl8168_mdio_write(tp, 0x14, 0x3002);
1796
+ rtl8168_mdio_write(tp, 0x14, 0x44dc);
1797
+ rtl8168_mdio_write(tp, 0x14, 0x3c00);
1798
+ rtl8168_mdio_write(tp, 0x14, 0x03aa);
1799
+ rtl8168_mdio_write(tp, 0x14, 0x2cbf);
1800
+ rtl8168_mdio_write(tp, 0x14, 0x8769);
1801
+ rtl8168_mdio_write(tp, 0x14, 0x0244);
1802
+ rtl8168_mdio_write(tp, 0x14, 0xdcad);
1803
+ rtl8168_mdio_write(tp, 0x14, 0x2823);
1804
+ rtl8168_mdio_write(tp, 0x14, 0xbf87);
1805
+ rtl8168_mdio_write(tp, 0x14, 0x6f02);
1806
+ rtl8168_mdio_write(tp, 0x14, 0x44dc);
1807
+ rtl8168_mdio_write(tp, 0x14, 0xad28);
1808
+ rtl8168_mdio_write(tp, 0x14, 0x1a02);
1809
+ rtl8168_mdio_write(tp, 0x14, 0x49ca);
1810
+ rtl8168_mdio_write(tp, 0x14, 0xef67);
1811
+ rtl8168_mdio_write(tp, 0x14, 0xd700);
1812
+ rtl8168_mdio_write(tp, 0x14, 0x0202);
1813
+ rtl8168_mdio_write(tp, 0x14, 0x49e5);
1814
+ rtl8168_mdio_write(tp, 0x14, 0xad50);
1815
+ rtl8168_mdio_write(tp, 0x14, 0xf7bf);
1816
+ rtl8168_mdio_write(tp, 0x14, 0x876c);
1817
+ rtl8168_mdio_write(tp, 0x14, 0x024a);
1818
+ rtl8168_mdio_write(tp, 0x14, 0x5fbf);
1819
+ rtl8168_mdio_write(tp, 0x14, 0x876c);
1820
+ rtl8168_mdio_write(tp, 0x14, 0x024a);
1821
+ rtl8168_mdio_write(tp, 0x14, 0x56ef);
1822
+ rtl8168_mdio_write(tp, 0x14, 0x95ff);
1823
+ rtl8168_mdio_write(tp, 0x14, 0xfefd);
1824
+ rtl8168_mdio_write(tp, 0x14, 0xfc04);
1825
+ rtl8168_mdio_write(tp, 0x14, 0xf8fa);
1826
+ rtl8168_mdio_write(tp, 0x14, 0xef69);
1827
+ rtl8168_mdio_write(tp, 0x14, 0xe080);
1828
+ rtl8168_mdio_write(tp, 0x14, 0x15ad);
1829
+ rtl8168_mdio_write(tp, 0x14, 0x2406);
1830
+ rtl8168_mdio_write(tp, 0x14, 0xbf87);
1831
+ rtl8168_mdio_write(tp, 0x14, 0x6002);
1832
+ rtl8168_mdio_write(tp, 0x14, 0x4a56);
1833
+ rtl8168_mdio_write(tp, 0x14, 0xef96);
1834
+ rtl8168_mdio_write(tp, 0x14, 0xfefc);
1835
+ rtl8168_mdio_write(tp, 0x14, 0x04f8);
1836
+ rtl8168_mdio_write(tp, 0x14, 0xe087);
1837
+ rtl8168_mdio_write(tp, 0x14, 0xf9e1);
1838
+ rtl8168_mdio_write(tp, 0x14, 0x87fa);
1839
+ rtl8168_mdio_write(tp, 0x14, 0x1b10);
1840
+ rtl8168_mdio_write(tp, 0x14, 0x9f1e);
1841
+ rtl8168_mdio_write(tp, 0x14, 0xee87);
1842
+ rtl8168_mdio_write(tp, 0x14, 0xf900);
1843
+ rtl8168_mdio_write(tp, 0x14, 0xe080);
1844
+ rtl8168_mdio_write(tp, 0x14, 0x15ac);
1845
+ rtl8168_mdio_write(tp, 0x14, 0x2606);
1846
+ rtl8168_mdio_write(tp, 0x14, 0xee87);
1847
+ rtl8168_mdio_write(tp, 0x14, 0xf700);
1848
+ rtl8168_mdio_write(tp, 0x14, 0xae12);
1849
+ rtl8168_mdio_write(tp, 0x14, 0x0286);
1850
+ rtl8168_mdio_write(tp, 0x14, 0x9702);
1851
+ rtl8168_mdio_write(tp, 0x14, 0x8565);
1852
+ rtl8168_mdio_write(tp, 0x14, 0x0285);
1853
+ rtl8168_mdio_write(tp, 0x14, 0x9d02);
1854
+ rtl8168_mdio_write(tp, 0x14, 0x865a);
1855
+ rtl8168_mdio_write(tp, 0x14, 0xae04);
1856
+ rtl8168_mdio_write(tp, 0x14, 0x10e4);
1857
+ rtl8168_mdio_write(tp, 0x14, 0x87f9);
1858
+ rtl8168_mdio_write(tp, 0x14, 0xfc04);
1859
+ rtl8168_mdio_write(tp, 0x14, 0xf8f9);
1860
+ rtl8168_mdio_write(tp, 0x14, 0xfaef);
1861
+ rtl8168_mdio_write(tp, 0x14, 0x69fa);
1862
+ rtl8168_mdio_write(tp, 0x14, 0xbf45);
1863
+ rtl8168_mdio_write(tp, 0x14, 0x3002);
1864
+ rtl8168_mdio_write(tp, 0x14, 0x44dc);
1865
+ rtl8168_mdio_write(tp, 0x14, 0xa103);
1866
+ rtl8168_mdio_write(tp, 0x14, 0x22e0);
1867
+ rtl8168_mdio_write(tp, 0x14, 0x87eb);
1868
+ rtl8168_mdio_write(tp, 0x14, 0xe187);
1869
+ rtl8168_mdio_write(tp, 0x14, 0xecef);
1870
+ rtl8168_mdio_write(tp, 0x14, 0x64bf);
1871
+ rtl8168_mdio_write(tp, 0x14, 0x8748);
1872
+ rtl8168_mdio_write(tp, 0x14, 0x0244);
1873
+ rtl8168_mdio_write(tp, 0x14, 0xdc1b);
1874
+ rtl8168_mdio_write(tp, 0x14, 0x46aa);
1875
+ rtl8168_mdio_write(tp, 0x14, 0x0abf);
1876
+ rtl8168_mdio_write(tp, 0x14, 0x874b);
1877
+ rtl8168_mdio_write(tp, 0x14, 0x0244);
1878
+ rtl8168_mdio_write(tp, 0x14, 0xdc1b);
1879
+ rtl8168_mdio_write(tp, 0x14, 0x46ab);
1880
+ rtl8168_mdio_write(tp, 0x14, 0x06bf);
1881
+ rtl8168_mdio_write(tp, 0x14, 0x8745);
1882
+ rtl8168_mdio_write(tp, 0x14, 0x024a);
1883
+ rtl8168_mdio_write(tp, 0x14, 0x5ffe);
1884
+ rtl8168_mdio_write(tp, 0x14, 0xef96);
1885
+ rtl8168_mdio_write(tp, 0x14, 0xfefd);
1886
+ rtl8168_mdio_write(tp, 0x14, 0xfc04);
1887
+ rtl8168_mdio_write(tp, 0x14, 0xf8f9);
1888
+ rtl8168_mdio_write(tp, 0x14, 0xef59);
1889
+ rtl8168_mdio_write(tp, 0x14, 0xf9bf);
1890
+ rtl8168_mdio_write(tp, 0x14, 0x4530);
1891
+ rtl8168_mdio_write(tp, 0x14, 0x0244);
1892
+ rtl8168_mdio_write(tp, 0x14, 0xdca1);
1893
+ rtl8168_mdio_write(tp, 0x14, 0x0310);
1894
+ rtl8168_mdio_write(tp, 0x14, 0xe087);
1895
+ rtl8168_mdio_write(tp, 0x14, 0xf7ac);
1896
+ rtl8168_mdio_write(tp, 0x14, 0x2605);
1897
+ rtl8168_mdio_write(tp, 0x14, 0x0285);
1898
+ rtl8168_mdio_write(tp, 0x14, 0xc9ae);
1899
+ rtl8168_mdio_write(tp, 0x14, 0x0d02);
1900
+ rtl8168_mdio_write(tp, 0x14, 0x860d);
1901
+ rtl8168_mdio_write(tp, 0x14, 0xae08);
1902
+ rtl8168_mdio_write(tp, 0x14, 0xe287);
1903
+ rtl8168_mdio_write(tp, 0x14, 0xf7f6);
1904
+ rtl8168_mdio_write(tp, 0x14, 0x36e6);
1905
+ rtl8168_mdio_write(tp, 0x14, 0x87f7);
1906
+ rtl8168_mdio_write(tp, 0x14, 0xfdef);
1907
+ rtl8168_mdio_write(tp, 0x14, 0x95fd);
1908
+ rtl8168_mdio_write(tp, 0x14, 0xfc04);
1909
+ rtl8168_mdio_write(tp, 0x14, 0xf8f9);
1910
+ rtl8168_mdio_write(tp, 0x14, 0xfafb);
1911
+ rtl8168_mdio_write(tp, 0x14, 0xef79);
1912
+ rtl8168_mdio_write(tp, 0x14, 0xfbbf);
1913
+ rtl8168_mdio_write(tp, 0x14, 0x8748);
1914
+ rtl8168_mdio_write(tp, 0x14, 0x0244);
1915
+ rtl8168_mdio_write(tp, 0x14, 0xdcef);
1916
+ rtl8168_mdio_write(tp, 0x14, 0x64e2);
1917
+ rtl8168_mdio_write(tp, 0x14, 0x87e9);
1918
+ rtl8168_mdio_write(tp, 0x14, 0xe387);
1919
+ rtl8168_mdio_write(tp, 0x14, 0xea1b);
1920
+ rtl8168_mdio_write(tp, 0x14, 0x659e);
1921
+ rtl8168_mdio_write(tp, 0x14, 0x10e4);
1922
+ rtl8168_mdio_write(tp, 0x14, 0x87e9);
1923
+ rtl8168_mdio_write(tp, 0x14, 0xe587);
1924
+ rtl8168_mdio_write(tp, 0x14, 0xeae2);
1925
+ rtl8168_mdio_write(tp, 0x14, 0x87f7);
1926
+ rtl8168_mdio_write(tp, 0x14, 0xf636);
1927
+ rtl8168_mdio_write(tp, 0x14, 0xe687);
1928
+ rtl8168_mdio_write(tp, 0x14, 0xf7ae);
1929
+ rtl8168_mdio_write(tp, 0x14, 0x13e2);
1930
+ rtl8168_mdio_write(tp, 0x14, 0x87f7);
1931
+ rtl8168_mdio_write(tp, 0x14, 0xf736);
1932
+ rtl8168_mdio_write(tp, 0x14, 0xe687);
1933
+ rtl8168_mdio_write(tp, 0x14, 0xf702);
1934
+ rtl8168_mdio_write(tp, 0x14, 0x49ca);
1935
+ rtl8168_mdio_write(tp, 0x14, 0xef57);
1936
+ rtl8168_mdio_write(tp, 0x14, 0xe687);
1937
+ rtl8168_mdio_write(tp, 0x14, 0xe7e7);
1938
+ rtl8168_mdio_write(tp, 0x14, 0x87e8);
1939
+ rtl8168_mdio_write(tp, 0x14, 0xffef);
1940
+ rtl8168_mdio_write(tp, 0x14, 0x97ff);
1941
+ rtl8168_mdio_write(tp, 0x14, 0xfefd);
1942
+ rtl8168_mdio_write(tp, 0x14, 0xfc04);
1943
+ rtl8168_mdio_write(tp, 0x14, 0xf8f9);
1944
+ rtl8168_mdio_write(tp, 0x14, 0xfafb);
1945
+ rtl8168_mdio_write(tp, 0x14, 0xef79);
1946
+ rtl8168_mdio_write(tp, 0x14, 0xfbe2);
1947
+ rtl8168_mdio_write(tp, 0x14, 0x87e7);
1948
+ rtl8168_mdio_write(tp, 0x14, 0xe387);
1949
+ rtl8168_mdio_write(tp, 0x14, 0xe8ef);
1950
+ rtl8168_mdio_write(tp, 0x14, 0x65e2);
1951
+ rtl8168_mdio_write(tp, 0x14, 0x87fb);
1952
+ rtl8168_mdio_write(tp, 0x14, 0xe387);
1953
+ rtl8168_mdio_write(tp, 0x14, 0xfcef);
1954
+ rtl8168_mdio_write(tp, 0x14, 0x7502);
1955
+ rtl8168_mdio_write(tp, 0x14, 0x49e5);
1956
+ rtl8168_mdio_write(tp, 0x14, 0xac50);
1957
+ rtl8168_mdio_write(tp, 0x14, 0x1abf);
1958
+ rtl8168_mdio_write(tp, 0x14, 0x8748);
1959
+ rtl8168_mdio_write(tp, 0x14, 0x0244);
1960
+ rtl8168_mdio_write(tp, 0x14, 0xdcef);
1961
+ rtl8168_mdio_write(tp, 0x14, 0x64e2);
1962
+ rtl8168_mdio_write(tp, 0x14, 0x87e9);
1963
+ rtl8168_mdio_write(tp, 0x14, 0xe387);
1964
+ rtl8168_mdio_write(tp, 0x14, 0xea1b);
1965
+ rtl8168_mdio_write(tp, 0x14, 0x659e);
1966
+ rtl8168_mdio_write(tp, 0x14, 0x16e4);
1967
+ rtl8168_mdio_write(tp, 0x14, 0x87e9);
1968
+ rtl8168_mdio_write(tp, 0x14, 0xe587);
1969
+ rtl8168_mdio_write(tp, 0x14, 0xeaae);
1970
+ rtl8168_mdio_write(tp, 0x14, 0x06bf);
1971
+ rtl8168_mdio_write(tp, 0x14, 0x8745);
1972
+ rtl8168_mdio_write(tp, 0x14, 0x024a);
1973
+ rtl8168_mdio_write(tp, 0x14, 0x5fe2);
1974
+ rtl8168_mdio_write(tp, 0x14, 0x87f7);
1975
+ rtl8168_mdio_write(tp, 0x14, 0xf636);
1976
+ rtl8168_mdio_write(tp, 0x14, 0xe687);
1977
+ rtl8168_mdio_write(tp, 0x14, 0xf7ff);
1978
+ rtl8168_mdio_write(tp, 0x14, 0xef97);
1979
+ rtl8168_mdio_write(tp, 0x14, 0xfffe);
1980
+ rtl8168_mdio_write(tp, 0x14, 0xfdfc);
1981
+ rtl8168_mdio_write(tp, 0x14, 0x04f8);
1982
+ rtl8168_mdio_write(tp, 0x14, 0xf9fa);
1983
+ rtl8168_mdio_write(tp, 0x14, 0xef69);
1984
+ rtl8168_mdio_write(tp, 0x14, 0xbf87);
1985
+ rtl8168_mdio_write(tp, 0x14, 0x3f02);
1986
+ rtl8168_mdio_write(tp, 0x14, 0x44dc);
1987
+ rtl8168_mdio_write(tp, 0x14, 0xad28);
1988
+ rtl8168_mdio_write(tp, 0x14, 0x29bf);
1989
+ rtl8168_mdio_write(tp, 0x14, 0x873c);
1990
+ rtl8168_mdio_write(tp, 0x14, 0x0244);
1991
+ rtl8168_mdio_write(tp, 0x14, 0xdcef);
1992
+ rtl8168_mdio_write(tp, 0x14, 0x54bf);
1993
+ rtl8168_mdio_write(tp, 0x14, 0x8739);
1994
+ rtl8168_mdio_write(tp, 0x14, 0x0244);
1995
+ rtl8168_mdio_write(tp, 0x14, 0xdcac);
1996
+ rtl8168_mdio_write(tp, 0x14, 0x290d);
1997
+ rtl8168_mdio_write(tp, 0x14, 0xac28);
1998
+ rtl8168_mdio_write(tp, 0x14, 0x05a3);
1999
+ rtl8168_mdio_write(tp, 0x14, 0x020c);
2000
+ rtl8168_mdio_write(tp, 0x14, 0xae10);
2001
+ rtl8168_mdio_write(tp, 0x14, 0xa303);
2002
+ rtl8168_mdio_write(tp, 0x14, 0x07ae);
2003
+ rtl8168_mdio_write(tp, 0x14, 0x0ba3);
2004
+ rtl8168_mdio_write(tp, 0x14, 0x0402);
2005
+ rtl8168_mdio_write(tp, 0x14, 0xae06);
2006
+ rtl8168_mdio_write(tp, 0x14, 0xbf87);
2007
+ rtl8168_mdio_write(tp, 0x14, 0x4502);
2008
+ rtl8168_mdio_write(tp, 0x14, 0x4a5f);
2009
+ rtl8168_mdio_write(tp, 0x14, 0xef96);
2010
+ rtl8168_mdio_write(tp, 0x14, 0xfefd);
2011
+ rtl8168_mdio_write(tp, 0x14, 0xfc04);
2012
+ rtl8168_mdio_write(tp, 0x14, 0xf8f9);
2013
+ rtl8168_mdio_write(tp, 0x14, 0xfafb);
2014
+ rtl8168_mdio_write(tp, 0x14, 0xef69);
2015
+ rtl8168_mdio_write(tp, 0x14, 0xfae0);
2016
+ rtl8168_mdio_write(tp, 0x14, 0x8015);
2017
+ rtl8168_mdio_write(tp, 0x14, 0xad25);
2018
+ rtl8168_mdio_write(tp, 0x14, 0x41d2);
2019
+ rtl8168_mdio_write(tp, 0x14, 0x0002);
2020
+ rtl8168_mdio_write(tp, 0x14, 0x86ed);
2021
+ rtl8168_mdio_write(tp, 0x14, 0xe087);
2022
+ rtl8168_mdio_write(tp, 0x14, 0xebe1);
2023
+ rtl8168_mdio_write(tp, 0x14, 0x87ec);
2024
+ rtl8168_mdio_write(tp, 0x14, 0x1b46);
2025
+ rtl8168_mdio_write(tp, 0x14, 0xab26);
2026
+ rtl8168_mdio_write(tp, 0x14, 0xd40b);
2027
+ rtl8168_mdio_write(tp, 0x14, 0xff1b);
2028
+ rtl8168_mdio_write(tp, 0x14, 0x46aa);
2029
+ rtl8168_mdio_write(tp, 0x14, 0x1fac);
2030
+ rtl8168_mdio_write(tp, 0x14, 0x3204);
2031
+ rtl8168_mdio_write(tp, 0x14, 0xef32);
2032
+ rtl8168_mdio_write(tp, 0x14, 0xae02);
2033
+ rtl8168_mdio_write(tp, 0x14, 0xd304);
2034
+ rtl8168_mdio_write(tp, 0x14, 0x0c31);
2035
+ rtl8168_mdio_write(tp, 0x14, 0xbf87);
2036
+ rtl8168_mdio_write(tp, 0x14, 0xeb1a);
2037
+ rtl8168_mdio_write(tp, 0x14, 0x93d8);
2038
+ rtl8168_mdio_write(tp, 0x14, 0x19d9);
2039
+ rtl8168_mdio_write(tp, 0x14, 0x1b46);
2040
+ rtl8168_mdio_write(tp, 0x14, 0xab0e);
2041
+ rtl8168_mdio_write(tp, 0x14, 0x19d8);
2042
+ rtl8168_mdio_write(tp, 0x14, 0x19d9);
2043
+ rtl8168_mdio_write(tp, 0x14, 0x1b46);
2044
+ rtl8168_mdio_write(tp, 0x14, 0xaa06);
2045
+ rtl8168_mdio_write(tp, 0x14, 0x12a2);
2046
+ rtl8168_mdio_write(tp, 0x14, 0x08c9);
2047
+ rtl8168_mdio_write(tp, 0x14, 0xae06);
2048
+ rtl8168_mdio_write(tp, 0x14, 0xbf87);
2049
+ rtl8168_mdio_write(tp, 0x14, 0x4202);
2050
+ rtl8168_mdio_write(tp, 0x14, 0x4a5f);
2051
+ rtl8168_mdio_write(tp, 0x14, 0xfeef);
2052
+ rtl8168_mdio_write(tp, 0x14, 0x96ff);
2053
+ rtl8168_mdio_write(tp, 0x14, 0xfefd);
2054
+ rtl8168_mdio_write(tp, 0x14, 0xfc04);
2055
+ rtl8168_mdio_write(tp, 0x14, 0xf8fb);
2056
+ rtl8168_mdio_write(tp, 0x14, 0xef79);
2057
+ rtl8168_mdio_write(tp, 0x14, 0xa200);
2058
+ rtl8168_mdio_write(tp, 0x14, 0x05bf);
2059
+ rtl8168_mdio_write(tp, 0x14, 0x8748);
2060
+ rtl8168_mdio_write(tp, 0x14, 0xae33);
2061
+ rtl8168_mdio_write(tp, 0x14, 0xa201);
2062
+ rtl8168_mdio_write(tp, 0x14, 0x05bf);
2063
+ rtl8168_mdio_write(tp, 0x14, 0x874b);
2064
+ rtl8168_mdio_write(tp, 0x14, 0xae2b);
2065
+ rtl8168_mdio_write(tp, 0x14, 0xa202);
2066
+ rtl8168_mdio_write(tp, 0x14, 0x05bf);
2067
+ rtl8168_mdio_write(tp, 0x14, 0x874e);
2068
+ rtl8168_mdio_write(tp, 0x14, 0xae23);
2069
+ rtl8168_mdio_write(tp, 0x14, 0xa203);
2070
+ rtl8168_mdio_write(tp, 0x14, 0x05bf);
2071
+ rtl8168_mdio_write(tp, 0x14, 0x8751);
2072
+ rtl8168_mdio_write(tp, 0x14, 0xae1b);
2073
+ rtl8168_mdio_write(tp, 0x14, 0xa204);
2074
+ rtl8168_mdio_write(tp, 0x14, 0x05bf);
2075
+ rtl8168_mdio_write(tp, 0x14, 0x8754);
2076
+ rtl8168_mdio_write(tp, 0x14, 0xae13);
2077
+ rtl8168_mdio_write(tp, 0x14, 0xa205);
2078
+ rtl8168_mdio_write(tp, 0x14, 0x05bf);
2079
+ rtl8168_mdio_write(tp, 0x14, 0x8757);
2080
+ rtl8168_mdio_write(tp, 0x14, 0xae0b);
2081
+ rtl8168_mdio_write(tp, 0x14, 0xa206);
2082
+ rtl8168_mdio_write(tp, 0x14, 0x05bf);
2083
+ rtl8168_mdio_write(tp, 0x14, 0x875a);
2084
+ rtl8168_mdio_write(tp, 0x14, 0xae03);
2085
+ rtl8168_mdio_write(tp, 0x14, 0xbf87);
2086
+ rtl8168_mdio_write(tp, 0x14, 0x5d02);
2087
+ rtl8168_mdio_write(tp, 0x14, 0x44dc);
2088
+ rtl8168_mdio_write(tp, 0x14, 0xef64);
2089
+ rtl8168_mdio_write(tp, 0x14, 0xef97);
2090
+ rtl8168_mdio_write(tp, 0x14, 0xfffc);
2091
+ rtl8168_mdio_write(tp, 0x14, 0x04af);
2092
+ rtl8168_mdio_write(tp, 0x14, 0x00ed);
2093
+ rtl8168_mdio_write(tp, 0x14, 0x54a4);
2094
+ rtl8168_mdio_write(tp, 0x14, 0x3474);
2095
+ rtl8168_mdio_write(tp, 0x14, 0xa600);
2096
+ rtl8168_mdio_write(tp, 0x14, 0x22a4);
2097
+ rtl8168_mdio_write(tp, 0x14, 0x3411);
2098
+ rtl8168_mdio_write(tp, 0x14, 0xb842);
2099
+ rtl8168_mdio_write(tp, 0x14, 0x22b8);
2100
+ rtl8168_mdio_write(tp, 0x14, 0x42f0);
2101
+ rtl8168_mdio_write(tp, 0x14, 0xa200);
2102
+ rtl8168_mdio_write(tp, 0x14, 0xf0a2);
2103
+ rtl8168_mdio_write(tp, 0x14, 0x02f0);
2104
+ rtl8168_mdio_write(tp, 0x14, 0xa204);
2105
+ rtl8168_mdio_write(tp, 0x14, 0xf0a2);
2106
+ rtl8168_mdio_write(tp, 0x14, 0x06f0);
2107
+ rtl8168_mdio_write(tp, 0x14, 0xa208);
2108
+ rtl8168_mdio_write(tp, 0x14, 0xf0a2);
2109
+ rtl8168_mdio_write(tp, 0x14, 0x0af0);
2110
+ rtl8168_mdio_write(tp, 0x14, 0xa20c);
2111
+ rtl8168_mdio_write(tp, 0x14, 0xf0a2);
2112
+ rtl8168_mdio_write(tp, 0x14, 0x0e55);
2113
+ rtl8168_mdio_write(tp, 0x14, 0xb820);
2114
+ rtl8168_mdio_write(tp, 0x14, 0xd9c6);
2115
+ rtl8168_mdio_write(tp, 0x14, 0x08aa);
2116
+ rtl8168_mdio_write(tp, 0x14, 0xc430);
2117
+ rtl8168_mdio_write(tp, 0x14, 0x00c6);
2118
+ rtl8168_mdio_write(tp, 0x14, 0x1433);
2119
+ rtl8168_mdio_write(tp, 0x14, 0xc41a);
2120
+ rtl8168_mdio_write(tp, 0x14, 0x88c4);
2121
+ rtl8168_mdio_write(tp, 0x14, 0x2e22);
2122
+ rtl8168_mdio_write(tp, 0x14, 0xc42e);
2123
+ rtl8168_mdio_write(tp, 0x14, 0x54c4);
2124
+ rtl8168_mdio_write(tp, 0x14, 0x1a00);
2125
+ rtl8168_mdio_write(tp, 0x13, 0xb818);
2126
+ rtl8168_mdio_write(tp, 0x14, 0x1a01);
2127
+ rtl8168_mdio_write(tp, 0x13, 0xb81a);
2128
+ rtl8168_mdio_write(tp, 0x14, 0x020b);
2129
+ rtl8168_mdio_write(tp, 0x13, 0xb81c);
2130
+ rtl8168_mdio_write(tp, 0x14, 0x03ce);
2131
+ rtl8168_mdio_write(tp, 0x13, 0xb81e);
2132
+ rtl8168_mdio_write(tp, 0x14, 0x00e7);
2133
+ rtl8168_mdio_write(tp, 0x13, 0xb846);
2134
+ rtl8168_mdio_write(tp, 0x14, 0xffff);
2135
+ rtl8168_mdio_write(tp, 0x13, 0xb848);
2136
+ rtl8168_mdio_write(tp, 0x14, 0xffff);
2137
+ rtl8168_mdio_write(tp, 0x13, 0xb84a);
2138
+ rtl8168_mdio_write(tp, 0x14, 0xffff);
2139
+ rtl8168_mdio_write(tp, 0x13, 0xb84c);
2140
+ rtl8168_mdio_write(tp, 0x14, 0xffff);
2141
+ rtl8168_mdio_write(tp, 0x13, 0xb832);
2142
+ rtl8168_mdio_write(tp, 0x14, 0x000f);
2143
+
2144
+
2145
+ rtl8168_mdio_write(tp, 0x1F, 0x0A43);
2146
+ rtl8168_mdio_write(tp, 0x13, 0x0000);
2147
+ rtl8168_mdio_write(tp, 0x14, 0x0000);
2148
+ rtl8168_mdio_write(tp, 0x1f, 0x0B82);
2149
+ gphy_val = rtl8168_mdio_read(tp, 0x17);
2150
+ gphy_val &= ~(BIT_0);
2151
+ rtl8168_mdio_write(tp, 0x17, gphy_val);
2152
+ rtl8168_mdio_write(tp, 0x1f, 0x0A43);
2153
+ rtl8168_mdio_write(tp, 0x13, 0x8042);
2154
+ rtl8168_mdio_write(tp, 0x14, 0x0000);
2155
+
2156
+ rtl8168_clear_phy_mcu_patch_request(tp);
2157
+
2158
+ if (tp->RequiredSecLanDonglePatch) {
2159
+ rtl8168_mdio_write(tp, 0x1F, 0x0A43);
2160
+ gphy_val = rtl8168_mdio_read(tp, 0x11);
2161
+ gphy_val &= ~BIT_6;
2162
+ rtl8168_mdio_write(tp, 0x11, gphy_val);
2163
+ }
2164
+}
2165
+
2166
+static void
2167
rtl8168_init_hw_phy_mcu(struct net_device *dev)
2168
{
2169
struct rtl8168_private *tp = netdev_priv(dev);
2170
2171
case CFG_METHOD_30:
2172
rtl8168_set_phy_mcu_8168h_2(dev);
2173
break;
2174
+ case CFG_METHOD_35:
2175
+ rtl8168_set_phy_mcu_8168h_3(dev);
2176
+ break;
2177
}
2178
2179
if (require_disable_phy_disable_mode)
2180
2181
}
2182
}
2183
} else if (tp->mcfg == CFG_METHOD_31 || tp->mcfg == CFG_METHOD_32 ||
2184
- tp->mcfg == CFG_METHOD_33) {
2185
+ tp->mcfg == CFG_METHOD_33 || tp->mcfg == CFG_METHOD_34) {
2186
rtl8168_mdio_write(tp, 0x1F, 0x0A43);
2187
rtl8168_mdio_write(tp, 0x13, 0x808E);
2188
ClearAndSetEthPhyBit( tp,
2189
2190
rtl8168_mdio_write(tp, 0x1F, 0x0000);
2191
}
2192
}
2193
+ } else if (tp->mcfg == CFG_METHOD_35) {
2194
+ rtl8168_mdio_write(tp, 0x1F, 0x0A44);
2195
+ rtl8168_set_eth_phy_bit(tp, 0x11, BIT_11);
2196
+ rtl8168_mdio_write(tp, 0x1F, 0x0000);
2197
+
2198
+
2199
+ rtl8168_mdio_write(tp, 0x1F, 0x0A4C);
2200
+ rtl8168_clear_eth_phy_bit(tp, 0x15, (BIT_14 | BIT_13));
2201
+ rtl8168_mdio_write(tp, 0x1F, 0x0000);
2202
+
2203
+
2204
+ rtl8168_mdio_write(tp, 0x1F, 0x0A43);
2205
+ rtl8168_mdio_write(tp, 0x13, 0x81B9);
2206
+ rtl8168_mdio_write(tp, 0x14, 0x2000);
2207
+ rtl8168_mdio_write(tp, 0x1F, 0x0000);
2208
+
2209
+
2210
+ rtl8168_mdio_write(tp, 0x1F, 0x0A43);
2211
+ rtl8168_mdio_write(tp, 0x13, 0x81D4);
2212
+ ClearAndSetEthPhyBit(tp,
2213
+ 0x14,
2214
+ 0xFF00,
2215
+ 0x6600);
2216
+ rtl8168_mdio_write(tp, 0x13, 0x81CB);
2217
+ ClearAndSetEthPhyBit(tp,
2218
+ 0x14,
2219
+ 0xFF00,
2220
+ 0x3500);
2221
+ rtl8168_mdio_write(tp, 0x1F, 0x0000);
2222
+
2223
+
2224
+ rtl8168_mdio_write(tp, 0x1F, 0x0A80);
2225
+ ClearAndSetEthPhyBit(tp,
2226
+ 0x16,
2227
+ 0x000F,
2228
+ 0x0005);
2229
+ rtl8168_mdio_write(tp, 0x1F, 0x0A43);
2230
+ rtl8168_mdio_write(tp, 0x13, 0x8016);
2231
+ rtl8168_set_eth_phy_bit(tp, 0x14, BIT_13);
2232
+ rtl8168_mdio_write(tp, 0x1F, 0x0000);
2233
+
2234
+ rtl8168_mdio_write(tp, 0x1F, 0x0A43);
2235
+ rtl8168_mdio_write(tp, 0x13, 0x811E);
2236
+ rtl8168_mdio_write(tp, 0x14, 0xDECA);
2237
+
2238
+ rtl8168_mdio_write(tp, 0x13, 0x811C);
2239
+ rtl8168_mdio_write(tp, 0x14, 0x8008);
2240
+ rtl8168_mdio_write(tp, 0x13, 0x8118);
2241
+ rtl8168_mdio_write(tp, 0x14, 0xF8B4);
2242
+ rtl8168_mdio_write(tp, 0x13, 0x811A);
2243
+ rtl8168_mdio_write(tp, 0x14, 0x1A04);
2244
+
2245
+ rtl8168_mdio_write(tp, 0x13, 0x8134);
2246
+ rtl8168_mdio_write(tp, 0x14, 0xDECA);
2247
+ rtl8168_mdio_write(tp, 0x13, 0x8132);
2248
+ rtl8168_mdio_write(tp, 0x14, 0xA008);
2249
+ rtl8168_mdio_write(tp, 0x13, 0x812E);
2250
+ rtl8168_mdio_write(tp, 0x14, 0x00B5);
2251
+ rtl8168_mdio_write(tp, 0x13, 0x8130);
2252
+ rtl8168_mdio_write(tp, 0x14, 0x1A04);
2253
+
2254
+ rtl8168_mdio_write(tp, 0x13, 0x8112);
2255
+ ClearAndSetEthPhyBit(tp,
2256
+ 0x14,
2257
+ 0xFF00,
2258
+ 0x7300);
2259
+ rtl8168_mdio_write(tp, 0x13, 0x8106);
2260
+ rtl8168_mdio_write(tp, 0x14, 0xA209);
2261
+ rtl8168_mdio_write(tp, 0x13, 0x8108);
2262
+ rtl8168_mdio_write(tp, 0x14, 0x13B0);
2263
+ rtl8168_mdio_write(tp, 0x13, 0x8103);
2264
+ ClearAndSetEthPhyBit(tp,
2265
+ 0x14,
2266
+ 0xF800,
2267
+ 0xB800);
2268
+ rtl8168_mdio_write(tp, 0x13, 0x8105);
2269
+ ClearAndSetEthPhyBit(tp,
2270
+ 0x14,
2271
+ 0xFF00,
2272
+ 0x0A00);
2273
+
2274
+
2275
+ rtl8168_mdio_write(tp, 0x1F, 0x0A43);
2276
+ rtl8168_mdio_write(tp, 0x13, 0x87EB);
2277
+ rtl8168_mdio_write(tp, 0x14, 0x0018);
2278
+ rtl8168_mdio_write(tp, 0x13, 0x87EB);
2279
+ rtl8168_mdio_write(tp, 0x14, 0x0018);
2280
+ rtl8168_mdio_write(tp, 0x13, 0x87ED);
2281
+ rtl8168_mdio_write(tp, 0x14, 0x0733);
2282
+ rtl8168_mdio_write(tp, 0x13, 0x87EF);
2283
+ rtl8168_mdio_write(tp, 0x14, 0x08DC);
2284
+ rtl8168_mdio_write(tp, 0x13, 0x87F1);
2285
+ rtl8168_mdio_write(tp, 0x14, 0x08DF);
2286
+ rtl8168_mdio_write(tp, 0x13, 0x87F3);
2287
+ rtl8168_mdio_write(tp, 0x14, 0x0C79);
2288
+ rtl8168_mdio_write(tp, 0x13, 0x87F5);
2289
+ rtl8168_mdio_write(tp, 0x14, 0x0D93);
2290
+ rtl8168_mdio_write(tp, 0x13, 0x87F9);
2291
+ rtl8168_mdio_write(tp, 0x14, 0x0010);
2292
+ rtl8168_mdio_write(tp, 0x13, 0x87FB);
2293
+ rtl8168_mdio_write(tp, 0x14, 0x0800);
2294
+ rtl8168_mdio_write(tp, 0x13, 0x8015);
2295
+ ClearAndSetEthPhyBit(tp,
2296
+ 0x14,
2297
+ 0x7000,
2298
+ 0x7000);
2299
+
2300
+
2301
+ rtl8168_mdio_write(tp, 0x1F, 0x0A43);
2302
+ rtl8168_mdio_write(tp, 0x13, 0x8111);
2303
+ ClearAndSetEthPhyBit(tp,
2304
+ 0x14,
2305
+ 0xFF00,
2306
+ 0x7C00);
2307
+ rtl8168_mdio_write(tp, 0x1F, 0x0000);
2308
+
2309
+ if (aspm) {
2310
+ if (HW_HAS_WRITE_PHY_MCU_RAM_CODE(tp)) {
2311
+ rtl8168_mdio_write(tp, 0x1F, 0x0A43);
2312
+ rtl8168_set_eth_phy_bit( tp, 0x10, BIT_2 );
2313
+ rtl8168_mdio_write(tp, 0x1F, 0x0000);
2314
+ }
2315
+ }
2316
}
2317
2318
#ifdef ENABLE_FIBER_SUPPORT
2319
if (HW_FIBER_MODE_ENABLED(tp))
2320
- rtl8168_hw_fiber_phy_config(dev);
2321
+ rtl8168_hw_fiber_phy_config(tp);
2322
#endif //ENABLE_FIBER_SUPPORT
2323
2324
//EthPhyPPSW
2325
2326
rtl8168_mdio_write(tp, 0x1F, 0x0000);
2327
} else if (tp->mcfg == CFG_METHOD_29 || tp->mcfg == CFG_METHOD_30 ||
2328
tp->mcfg == CFG_METHOD_31 || tp->mcfg == CFG_METHOD_32 ||
2329
- tp->mcfg == CFG_METHOD_33) {
2330
+ tp->mcfg == CFG_METHOD_33 || tp->mcfg == CFG_METHOD_34 ||
2331
+ tp->mcfg == CFG_METHOD_35) {
2332
//enable EthPhyPPSW
2333
rtl8168_mdio_write(tp, 0x1F, 0x0A44);
2334
rtl8168_set_eth_phy_bit( tp, 0x11, BIT_7 );
2335
2336
tp->mcfg == CFG_METHOD_27 || tp->mcfg == CFG_METHOD_28 ||
2337
tp->mcfg == CFG_METHOD_29 || tp->mcfg == CFG_METHOD_30 ||
2338
tp->mcfg == CFG_METHOD_31 || tp->mcfg == CFG_METHOD_32 ||
2339
- tp->mcfg == CFG_METHOD_33) {
2340
+ tp->mcfg == CFG_METHOD_33 || tp->mcfg == CFG_METHOD_34 ||
2341
+ tp->mcfg == CFG_METHOD_35) {
2342
if (aspm)
2343
rtl8168_enable_ocp_phy_power_saving(dev);
2344
}
2345
2346
case CFG_METHOD_31:
2347
case CFG_METHOD_32:
2348
case CFG_METHOD_33:
2349
+ case CFG_METHOD_34:
2350
+ case CFG_METHOD_35:
2351
tp->bios_setting = RTL_R32(tp, 0x8c);
2352
break;
2353
}
2354
2355
case CFG_METHOD_31:
2356
case CFG_METHOD_32:
2357
case CFG_METHOD_33:
2358
+ case CFG_METHOD_34:
2359
+ case CFG_METHOD_35:
2360
RTL_W32(tp, 0x8C, tp->bios_setting);
2361
break;
2362
}
2363
2364
2365
rtl8168_get_bios_setting(dev);
2366
2367
+ tp->num_rx_desc = NUM_RX_DESC;
2368
+ tp->num_tx_desc = NUM_TX_DESC;
2369
+
2370
switch (tp->mcfg) {
2371
case CFG_METHOD_11:
2372
case CFG_METHOD_12:
2373
2374
case CFG_METHOD_31:
2375
case CFG_METHOD_32:
2376
case CFG_METHOD_33:
2377
+ case CFG_METHOD_34:
2378
tp->HwSuppDashVer = 3;
2379
break;
2380
default:
2381
2382
case CFG_METHOD_31:
2383
case CFG_METHOD_32:
2384
case CFG_METHOD_33:
2385
+ case CFG_METHOD_34:
2386
tp->HwPkgDet = rtl8168_mac_ocp_read(tp, 0xDC00);
2387
tp->HwPkgDet = (tp->HwPkgDet >> 3) & 0x0F;
2388
break;
2389
2390
case CFG_METHOD_31:
2391
case CFG_METHOD_32:
2392
case CFG_METHOD_33:
2393
+ case CFG_METHOD_34:
2394
+ case CFG_METHOD_35:
2395
tp->HwSuppNowIsOobVer = 1;
2396
break;
2397
}
2398
2399
case CFG_METHOD_31:
2400
case CFG_METHOD_32:
2401
case CFG_METHOD_33:
2402
+ case CFG_METHOD_34:
2403
+ case CFG_METHOD_35:
2404
tp->HwSuppPhyOcpVer = 1;
2405
break;
2406
}
2407
2408
case CFG_METHOD_31:
2409
case CFG_METHOD_32:
2410
case CFG_METHOD_33:
2411
+ case CFG_METHOD_34:
2412
+ case CFG_METHOD_35:
2413
tp->HwSuppUpsVer = 1;
2414
break;
2415
}
2416
2417
case CFG_METHOD_31:
2418
case CFG_METHOD_32:
2419
case CFG_METHOD_33:
2420
+ case CFG_METHOD_34:
2421
tp->HwPcieSNOffset = 0x16C;
2422
break;
2423
case CFG_METHOD_DEFAULT:
2424
2425
case CFG_METHOD_31:
2426
case CFG_METHOD_32:
2427
case CFG_METHOD_33:
2428
+ case CFG_METHOD_34:
2429
+ case CFG_METHOD_35:
2430
tp->HwSuppAspmClkIntrLock = 1;
2431
break;
2432
}
2433
2434
case CFG_METHOD_31:
2435
case CFG_METHOD_32:
2436
case CFG_METHOD_33:
2437
+ case CFG_METHOD_34:
2438
+ case CFG_METHOD_35:
2439
tp->org_pci_offset_99 = rtl8168_csi_fun0_read_byte(tp, 0x99);
2440
tp->org_pci_offset_99 &= ~(BIT_5|BIT_6);
2441
break;
2442
2443
case CFG_METHOD_28:
2444
case CFG_METHOD_29:
2445
case CFG_METHOD_30:
2446
+ case CFG_METHOD_35:
2447
tp->org_pci_offset_180 = rtl8168_csi_fun0_read_byte(tp, 0x180);
2448
break;
2449
case CFG_METHOD_31:
2450
case CFG_METHOD_32:
2451
case CFG_METHOD_33:
2452
+ case CFG_METHOD_34:
2453
tp->org_pci_offset_180 = rtl8168_csi_fun0_read_byte(tp, 0x214);
2454
break;
2455
}
2456
2457
case CFG_METHOD_25:
2458
case CFG_METHOD_27:
2459
case CFG_METHOD_28:
2460
+ case CFG_METHOD_31:
2461
+ case CFG_METHOD_32:
2462
+ case CFG_METHOD_33:
2463
+ case CFG_METHOD_34:
2464
if (tp->org_pci_offset_99 & BIT_2)
2465
tp->issue_offset_99_event = TRUE;
2466
break;
2467
2468
case CFG_METHOD_30:
2469
case CFG_METHOD_31:
2470
case CFG_METHOD_32:
2471
- case CFG_METHOD_33: {
2472
+ case CFG_METHOD_33:
2473
+ case CFG_METHOD_34: {
2474
u16 rg_saw_cnt;
2475
2476
rtl8168_mdio_write(tp, 0x1F, 0x0C42);
2477
2478
rg_saw_cnt &= ~(BIT_15|BIT_14);
2479
rtl8168_mdio_write(tp, 0x1F, 0x0000);
2480
2481
- if ( rg_saw_cnt > 0) {
2482
+ if (rg_saw_cnt > 0) {
2483
tp->SwrCnt1msIni = 16000000/rg_saw_cnt;
2484
tp->SwrCnt1msIni &= 0x0FFF;
2485
2486
2487
}
2488
2489
#ifdef ENABLE_FIBER_SUPPORT
2490
- rtl8168_check_hw_fiber_mode_support(dev);
2491
+ rtl8168_check_hw_fiber_mode_support(tp);
2492
#endif //ENABLE_FIBER_SUPPORT
2493
2494
switch(tp->mcfg) {
2495
case CFG_METHOD_32:
2496
case CFG_METHOD_33:
2497
+ case CFG_METHOD_34:
2498
if (tp->HwPkgDet == 0x06) {
2499
u8 tmpUchar = rtl8168_eri_read(tp, 0xE6, 1, ERIAR_ExGMAC);
2500
if (tmpUchar == 0x02)
2501
2502
hwoptimize |= HW_PATCH_SAMSUNG_LAN_DONGLE;
2503
}
2504
2505
+#ifdef CONFIG_CTAP_SHORT_OFF
2506
+ hwoptimize |= HW_PATCH_SAMSUNG_LAN_DONGLE;
2507
+#endif //CONFIG_CTAP_SHORT_OFF
2508
+
2509
if (hwoptimize & HW_PATCH_SAMSUNG_LAN_DONGLE) {
2510
switch (tp->mcfg) {
2511
case CFG_METHOD_14:
2512
2513
case CFG_METHOD_31:
2514
case CFG_METHOD_32:
2515
case CFG_METHOD_33:
2516
+ case CFG_METHOD_34:
2517
+ case CFG_METHOD_35:
2518
tp->HwSuppMagicPktVer = WAKEUP_MAGIC_PACKET_V2;
2519
break;
2520
case CFG_METHOD_DEFAULT:
2521
2522
case CFG_METHOD_30:
2523
tp->HwSuppEsdVer = 2;
2524
break;
2525
+ case CFG_METHOD_35:
2526
+ tp->HwSuppEsdVer = 3;
2527
+ break;
2528
default:
2529
tp->HwSuppEsdVer = 1;
2530
break;
2531
}
2532
2533
- if (tp->HwSuppEsdVer == 2) {
2534
+ if (tp->HwSuppEsdVer == 2 ||
2535
+ tp->HwSuppEsdVer == 3) {
2536
rtl8168_mdio_write(tp, 0x1F, 0x0A46);
2537
tp->BackupPhyFuseDout_15_0 = rtl8168_mdio_read(tp, 0x10);
2538
+ tp->BackupPhyFuseDout_31_16 = rtl8168_mdio_read(tp, 0x11);
2539
tp->BackupPhyFuseDout_47_32 = rtl8168_mdio_read(tp, 0x12);
2540
tp->BackupPhyFuseDout_63_48 = rtl8168_mdio_read(tp, 0x13);
2541
rtl8168_mdio_write(tp, 0x1F, 0x0000);
2542
2543
case CFG_METHOD_26:
2544
case CFG_METHOD_29:
2545
case CFG_METHOD_30:
2546
+ case CFG_METHOD_35:
2547
tp->HwSuppCheckPhyDisableModeVer = 2;
2548
break;
2549
case CFG_METHOD_23:
2550
2551
case CFG_METHOD_31:
2552
case CFG_METHOD_32:
2553
case CFG_METHOD_33:
2554
+ case CFG_METHOD_34:
2555
tp->HwSuppCheckPhyDisableModeVer = 3;
2556
break;
2557
}
2558
2559
case CFG_METHOD_31:
2560
case CFG_METHOD_32:
2561
case CFG_METHOD_33:
2562
+ case CFG_METHOD_34:
2563
tp->sw_ram_code_ver = NIC_RAMCODE_VERSION_CFG_METHOD_31;
2564
break;
2565
+ case CFG_METHOD_35:
2566
+ tp->sw_ram_code_ver = NIC_RAMCODE_VERSION_CFG_METHOD_35;
2567
+ break;
2568
}
2569
2570
if (tp->HwIcVerUnknown) {
2571
2572
tp->speed = speed_mode;
2573
tp->duplex = duplex_mode;
2574
tp->advertising = advertising_mode;
2575
+ tp->fcpause = rtl8168_fc_full;
2576
2577
tp->max_jumbo_frame_size = rtl_chip_infotp->chipset.jumbo_frame_sz;
2578
#if LINUX_VERSION_CODE >= KERNEL_VERSION(4,10,0)
2579
2580
2581
#ifdef ENABLE_FIBER_SUPPORT
2582
if (HW_FIBER_MODE_ENABLED(tp))
2583
- rtl8168_set_fiber_mode_software_variable(dev);
2584
+ rtl8168_set_fiber_mode_software_variable(tp);
2585
#endif //ENABLE_FIBER_SUPPORT
2586
}
2587
2588
2589
free_netdev(dev);
2590
}
2591
2592
+static void
2593
+rtl8168_hw_address_set(struct net_device *dev, u8 mac_addrMAC_ADDR_LEN)
2594
+{
2595
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,17,0)
2596
+ eth_hw_addr_set(dev, mac_addr);
2597
+#else
2598
+ memcpy(dev->dev_addr, mac_addr, MAC_ADDR_LEN);
2599
+#endif //LINUX_VERSION_CODE >= KERNEL_VERSION(5,17,0)
2600
+}
2601
+
2602
static int
2603
rtl8168_get_mac_address(struct net_device *dev)
2604
{
2605
2606
tp->mcfg == CFG_METHOD_30 ||
2607
tp->mcfg == CFG_METHOD_31 ||
2608
tp->mcfg == CFG_METHOD_32 ||
2609
- tp->mcfg == CFG_METHOD_33) {
2610
+ tp->mcfg == CFG_METHOD_33 ||
2611
+ tp->mcfg == CFG_METHOD_34 ||
2612
+ tp->mcfg == CFG_METHOD_35) {
2613
*(u32*)&mac_addr0 = rtl8168_eri_read(tp, 0xE0, 4, ERIAR_ExGMAC);
2614
*(u16*)&mac_addr4 = rtl8168_eri_read(tp, 0xE4, 2, ERIAR_ExGMAC);
2615
} else {
2616
2617
tp->mcfg == CFG_METHOD_30 ||
2618
tp->mcfg == CFG_METHOD_31 ||
2619
tp->mcfg == CFG_METHOD_32 ||
2620
- tp->mcfg == CFG_METHOD_33) {
2621
+ tp->mcfg == CFG_METHOD_33 ||
2622
+ tp->mcfg == CFG_METHOD_34 ||
2623
+ tp->mcfg == CFG_METHOD_35) {
2624
*pUshort++ = rtl8168_eeprom_read_sc(tp, 1);
2625
*pUshort++ = rtl8168_eeprom_read_sc(tp, 2);
2626
*pUshort = rtl8168_eeprom_read_sc(tp, 3);
2627
2628
if (!is_valid_ether_addr(mac_addr)) {
2629
netif_err(tp, probe, dev, "Invalid ether addr %pM\n",
2630
mac_addr);
2631
- eth_hw_addr_random(dev);
2632
- ether_addr_copy(mac_addr, dev->dev_addr);
2633
+ eth_random_addr(mac_addr);
2634
+ dev->addr_assign_type = NET_ADDR_RANDOM;
2635
netif_info(tp, probe, dev, "Random ether addr %pM\n",
2636
mac_addr);
2637
tp->random_mac = 1;
2638
}
2639
2640
+ rtl8168_hw_address_set(dev, mac_addr);
2641
rtl8168_rar_set(tp, mac_addr);
2642
2643
- for (i = 0; i < MAC_ADDR_LEN; i++) {
2644
- dev->dev_addri = RTL_R8(tp, MAC0 + i);
2645
- tp->org_mac_addri = dev->dev_addri; /* keep the original MAC address */
2646
- }
2647
+ /* keep the original MAC address */
2648
+ memcpy(tp->org_mac_addr, dev->dev_addr, MAC_ADDR_LEN);
2649
#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,13)
2650
memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
2651
#endif
2652
-// memcpy(dev->dev_addr, dev->dev_addr, dev->addr_len);
2653
-
2654
return 0;
2655
}
2656
2657
2658
2659
spin_lock_irqsave(&tp->lock, flags);
2660
2661
- memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2662
+ rtl8168_hw_address_set(dev, addr->sa_data);
2663
2664
rtl8168_rar_set(tp, dev->dev_addr);
2665
2666
2667
*****************************************************************************/
2668
void
2669
rtl8168_rar_set(struct rtl8168_private *tp,
2670
- uint8_t *addr)
2671
+ const u8 *addr)
2672
{
2673
uint32_t rar_low = 0;
2674
uint32_t rar_high = 0;
2675
2676
}
2677
#endif //ETHTOOL_OPS_COMPAT
2678
2679
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,15,0)
2680
+static int rtl8168_siocdevprivate(struct net_device *dev, struct ifreq *ifr,
2681
+ void __user *data, int cmd)
2682
+{
2683
+ struct rtl8168_private *tp = netdev_priv(dev);
2684
+ int ret = 0;
2685
+
2686
+ switch (cmd) {
2687
+ case SIOCDEVPRIVATE_RTLASF:
2688
+ if (!netif_running(dev)) {
2689
+ ret = -ENODEV;
2690
+ break;
2691
+ }
2692
+
2693
+ ret = rtl8168_asf_ioctl(dev, ifr);
2694
+ break;
2695
+
2696
+#ifdef ENABLE_DASH_SUPPORT
2697
+ case SIOCDEVPRIVATE_RTLDASH:
2698
+ if (!netif_running(dev)) {
2699
+ ret = -ENODEV;
2700
+ break;
2701
+ }
2702
+
2703
+ if (!capable(CAP_NET_ADMIN)) {
2704
+ ret = -EPERM;
2705
+ break;
2706
+ }
2707
+
2708
+ ret = rtl8168_dash_ioctl(dev, ifr);
2709
+ break;
2710
+#endif
2711
+
2712
+#ifdef ENABLE_REALWOW_SUPPORT
2713
+ case SIOCDEVPRIVATE_RTLREALWOW:
2714
+ if (!netif_running(dev)) {
2715
+ ret = -ENODEV;
2716
+ break;
2717
+ }
2718
+
2719
+ if (!capable(CAP_NET_ADMIN)) {
2720
+ ret = -EPERM;
2721
+ break;
2722
+ }
2723
+
2724
+ ret = rtl8168_realwow_ioctl(dev, ifr);
2725
+ break;
2726
+#endif
2727
+
2728
+ case SIOCRTLTOOL:
2729
+ if (!capable(CAP_NET_ADMIN)) {
2730
+ ret = -EPERM;
2731
+ break;
2732
+ }
2733
+
2734
+ ret = rtl8168_tool_ioctl(tp, ifr);
2735
+ break;
2736
+
2737
+ default:
2738
+ ret = -EOPNOTSUPP;
2739
+ }
2740
+
2741
+ return ret;
2742
+}
2743
+#endif //LINUX_VERSION_CODE >= KERNEL_VERSION(5,15,0)
2744
+
2745
static int
2746
rtl8168_do_ioctl(struct net_device *dev,
2747
struct ifreq *ifr,
2748
2749
break;
2750
}
2751
2752
+ if (!capable(CAP_NET_ADMIN)) {
2753
+ ret = -EPERM;
2754
+ break;
2755
+ }
2756
+
2757
ret = rtl8168_realwow_ioctl(dev, ifr);
2758
break;
2759
#endif
2760
2761
case SIOCRTLTOOL:
2762
+ if (!capable(CAP_NET_ADMIN)) {
2763
+ ret = -EPERM;
2764
+ break;
2765
+ }
2766
+
2767
ret = rtl8168_tool_ioctl(tp, ifr);
2768
break;
2769
2770
2771
case CFG_METHOD_15:
2772
case CFG_METHOD_29:
2773
case CFG_METHOD_30:
2774
+ case CFG_METHOD_35:
2775
rtl8168_mdio_write(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
2776
break;
2777
case CFG_METHOD_21:
2778
2779
printk(KERN_ERR "%s: cmd = 0x%02x, should be 0x%02x \n.", dev->name, cmd, tp->pci_cfg_space.cmd);
2780
pci_write_config_byte(pdev, PCI_COMMAND, tp->pci_cfg_space.cmd);
2781
tp->esd_flag |= BIT_0;
2782
+
2783
+ pci_read_config_byte(pdev, PCI_COMMAND, &cmd);
2784
+ if (cmd == 0xff) {
2785
+ printk(KERN_ERR "%s: pci link is down \n.", dev->name);
2786
+ goto out_unlock;
2787
+ }
2788
}
2789
2790
pci_read_config_word(pdev, PCI_BASE_ADDRESS_0, &io_base_l);
2791
2792
rtl8168_set_speed(dev, tp->autoneg, tp->speed, tp->duplex, tp->advertising);
2793
tp->esd_flag = 0;
2794
}
2795
+
2796
+out_unlock:
2797
spin_unlock_irqrestore(&tp->lock, flags);
2798
2799
mod_timer(timer, jiffies + timeout);
2800
2801
.ndo_tx_timeout = rtl8168_tx_timeout,
2802
.ndo_change_mtu = rtl8168_change_mtu,
2803
.ndo_set_mac_address = rtl8168_set_mac_address,
2804
+#if LINUX_VERSION_CODE < KERNEL_VERSION(5,15,0)
2805
.ndo_do_ioctl = rtl8168_do_ioctl,
2806
+#else
2807
+ .ndo_siocdevprivate = rtl8168_siocdevprivate,
2808
+ .ndo_eth_ioctl = rtl8168_do_ioctl,
2809
+#endif //LINUX_VERSION_CODE < KERNEL_VERSION(5,15,0)
2810
#if LINUX_VERSION_CODE < KERNEL_VERSION(3,1,0)
2811
.ndo_set_multicast_list = rtl8168_set_rx_mode,
2812
#else
2813
2814
/* Get production from EEPROM */
2815
if (((tp->mcfg == CFG_METHOD_21 || tp->mcfg == CFG_METHOD_22 ||
2816
tp->mcfg == CFG_METHOD_25 || tp->mcfg == CFG_METHOD_29 ||
2817
- tp->mcfg == CFG_METHOD_30) && (rtl8168_mac_ocp_read(tp, 0xDC00) & BIT_3)) ||
2818
+ tp->mcfg == CFG_METHOD_30 || tp->mcfg == CFG_METHOD_35) &&
2819
+ (rtl8168_mac_ocp_read(tp, 0xDC00) & BIT_3)) ||
2820
((tp->mcfg == CFG_METHOD_26) && (rtl8168_mac_ocp_read(tp, 0xDC00) & BIT_4)))
2821
tp->eeprom_type = EEPROM_TYPE_NONE;
2822
else
2823
2824
* Rx and Tx descriptors needs 256 bytes alignment.
2825
* pci_alloc_consistent provides more.
2826
*/
2827
- tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8168_TX_RING_BYTES,
2828
+ tp->TxDescArray = dma_alloc_coherent(&pdev->dev,
2829
+ (tp->num_tx_desc * sizeof(struct TxDesc)),
2830
&tp->TxPhyAddr, GFP_KERNEL);
2831
if (!tp->TxDescArray)
2832
goto err_free_all_allocated_mem;
2833
2834
- tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8168_RX_RING_BYTES,
2835
+ tp->RxDescArray = dma_alloc_coherent(&pdev->dev,
2836
+ (tp->num_rx_desc * sizeof(struct RxDesc)),
2837
&tp->RxPhyAddr, GFP_KERNEL);
2838
if (!tp->RxDescArray)
2839
goto err_free_all_allocated_mem;
2840
2841
2842
err_free_all_allocated_mem:
2843
if (tp->RxDescArray != NULL) {
2844
- dma_free_coherent(&pdev->dev, R8168_RX_RING_BYTES, tp->RxDescArray,
2845
+ dma_free_coherent(&pdev->dev,
2846
+ (tp->num_rx_desc * sizeof(struct RxDesc)),
2847
+ tp->RxDescArray,
2848
tp->RxPhyAddr);
2849
tp->RxDescArray = NULL;
2850
}
2851
2852
if (tp->TxDescArray != NULL) {
2853
- dma_free_coherent(&pdev->dev, R8168_TX_RING_BYTES, tp->TxDescArray,
2854
+ dma_free_coherent(&pdev->dev,
2855
+ (tp->num_tx_desc * sizeof(struct TxDesc)),
2856
+ tp->TxDescArray,
2857
tp->TxPhyAddr);
2858
tp->TxDescArray = NULL;
2859
}
2860
2861
case CFG_METHOD_31:
2862
case CFG_METHOD_32:
2863
case CFG_METHOD_33:
2864
+ case CFG_METHOD_34:
2865
+ case CFG_METHOD_35:
2866
RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~BIT_1);
2867
break;
2868
}
2869
2870
case CFG_METHOD_31:
2871
case CFG_METHOD_32:
2872
case CFG_METHOD_33:
2873
+ case CFG_METHOD_34:
2874
+ case CFG_METHOD_35:
2875
csi_tmp = rtl8168_eri_read(tp, 0xDE, 1, ERIAR_ExGMAC);
2876
csi_tmp &= BIT_0;
2877
rtl8168_eri_write(tp, 0xDE, 1, csi_tmp, ERIAR_ExGMAC);
2878
2879
} else if (tp->mcfg == CFG_METHOD_21 || tp->mcfg == CFG_METHOD_22 ||
2880
tp->mcfg == CFG_METHOD_24 || tp->mcfg == CFG_METHOD_25 ||
2881
tp->mcfg == CFG_METHOD_26 || tp->mcfg == CFG_METHOD_29 ||
2882
- tp->mcfg == CFG_METHOD_30) {
2883
+ tp->mcfg == CFG_METHOD_30 || tp->mcfg == CFG_METHOD_35) {
2884
set_offset70F(tp, 0x27);
2885
set_offset79(tp, 0x50);
2886
if (tp->mcfg == CFG_METHOD_21 || tp->mcfg == CFG_METHOD_22)
2887
2888
csi_tmp |= BIT_0;
2889
rtl8168_eri_write(tp, 0xDC, 1, csi_tmp, ERIAR_ExGMAC);
2890
2891
+ if (tp->mcfg == CFG_METHOD_35)
2892
+ rtl8168_set_mcu_ocp_bit(tp, 0xD438, (BIT_1 | BIT_0));
2893
+
2894
if (tp->mcfg == CFG_METHOD_26) {
2895
mac_ocp_data = rtl8168_mac_ocp_read(tp, 0xD3C0);
2896
mac_ocp_data &= ~(BIT_11 | BIT_10 | BIT_9 | BIT_8 | BIT_7 | BIT_6 | BIT_5 | BIT_4 | BIT_3 | BIT_2 | BIT_1 | BIT_0);
2897
2898
mac_ocp_data = rtl8168_mac_ocp_read(tp, 0xD3C4);
2899
mac_ocp_data |= BIT_0;
2900
rtl8168_mac_ocp_write(tp, 0xD3C4, mac_ocp_data);
2901
- } else if (tp->mcfg == CFG_METHOD_29 || tp->mcfg == CFG_METHOD_30) {
2902
+ } else if (tp->mcfg == CFG_METHOD_29 || tp->mcfg == CFG_METHOD_30 ||
2903
+ tp->mcfg == CFG_METHOD_35) {
2904
2905
if (tp->RequireAdjustUpsTxLinkPulseTiming) {
2906
mac_ocp_data = rtl8168_mac_ocp_read(tp, 0xD412);
2907
2908
rtl8168_eri_write(tp, 0xC0, 2, 0x0000, ERIAR_ExGMAC);
2909
rtl8168_eri_write(tp, 0xB8, 4, 0x00000000, ERIAR_ExGMAC);
2910
2911
- if (tp->mcfg == CFG_METHOD_29 || tp->mcfg == CFG_METHOD_30) {
2912
+ if (tp->mcfg == CFG_METHOD_29 || tp->mcfg == CFG_METHOD_30 ||
2913
+ tp->mcfg == CFG_METHOD_35) {
2914
rtl8168_mac_ocp_write(tp, 0xE054, 0x0000);
2915
2916
rtl8168_eri_write(tp, 0x5F0, 2, 0x4000, ERIAR_ExGMAC);
2917
2918
rtl8168_eri_write(tp, 0x5F0, 2, 0x4F87, ERIAR_ExGMAC);
2919
}
2920
2921
- if (tp->mcfg == CFG_METHOD_29 || tp->mcfg == CFG_METHOD_30) {
2922
+ if (tp->mcfg == CFG_METHOD_29 || tp->mcfg == CFG_METHOD_30 ||
2923
+ tp->mcfg == CFG_METHOD_35) {
2924
csi_tmp = rtl8168_eri_read(tp, 0xDC, 4, ERIAR_ExGMAC);
2925
csi_tmp |= (BIT_2 | BIT_3 | BIT_4);
2926
rtl8168_eri_write(tp, 0xDC, 4, csi_tmp, ERIAR_ExGMAC);
2927
2928
if (tp->mcfg == CFG_METHOD_21 || tp->mcfg == CFG_METHOD_22 ||
2929
tp->mcfg == CFG_METHOD_24 || tp->mcfg == CFG_METHOD_25) {
2930
rtl8168_mac_ocp_write(tp, 0xC140, 0xFFFF);
2931
- } else if (tp->mcfg == CFG_METHOD_29 || tp->mcfg == CFG_METHOD_30) {
2932
+ } else if (tp->mcfg == CFG_METHOD_29 || tp->mcfg == CFG_METHOD_30 ||
2933
+ tp->mcfg == CFG_METHOD_35) {
2934
rtl8168_mac_ocp_write(tp, 0xC140, 0xFFFF);
2935
rtl8168_mac_ocp_write(tp, 0xC142, 0xFFFF);
2936
}
2937
2938
csi_tmp &= ~BIT_12;
2939
rtl8168_eri_write(tp, 0x1B0, 4, csi_tmp, ERIAR_ExGMAC);
2940
2941
- if (tp->mcfg == CFG_METHOD_29 || tp->mcfg == CFG_METHOD_30) {
2942
+ if (tp->mcfg == CFG_METHOD_29 || tp->mcfg == CFG_METHOD_30 ||
2943
+ tp->mcfg == CFG_METHOD_35) {
2944
csi_tmp = rtl8168_eri_read(tp, 0x2FC, 1, ERIAR_ExGMAC);
2945
csi_tmp &= ~(BIT_2);
2946
rtl8168_eri_write(tp, 0x2FC, 1, csi_tmp, ERIAR_ExGMAC);
2947
2948
rtl8168_mac_ocp_write(tp, 0xE860, mac_ocp_data);
2949
}
2950
} else if (tp->mcfg == CFG_METHOD_31 || tp->mcfg == CFG_METHOD_32 ||
2951
- tp->mcfg == CFG_METHOD_33) {
2952
+ tp->mcfg == CFG_METHOD_33 || tp->mcfg == CFG_METHOD_34) {
2953
set_offset70F(tp, 0x27);
2954
set_offset79(tp, 0x50);
2955
2956
2957
2958
mac_ocp_data = rtl8168_mac_ocp_read(tp, 0xE056);
2959
mac_ocp_data &= ~(BIT_7 | BIT_6 | BIT_5 | BIT_4);
2960
+ if (tp->HwPkgDet == 0x0F)
2961
+ mac_ocp_data |= (BIT_6 | BIT_5 | BIT_4);
2962
rtl8168_mac_ocp_write(tp, 0xE056, mac_ocp_data);
2963
- if (FALSE == HW_SUPP_SERDES_PHY(tp))
2964
+ if (tp->HwPkgDet == 0x0F)
2965
rtl8168_mac_ocp_write(tp, 0xEA80, 0x0003);
2966
else
2967
rtl8168_mac_ocp_write(tp, 0xEA80, 0x0000);
2968
2969
rtl8168_oob_mutex_lock(tp);
2970
mac_ocp_data = rtl8168_mac_ocp_read(tp, 0xE052);
2971
mac_ocp_data &= ~(BIT_3 | BIT_0);
2972
+ if (tp->HwPkgDet == 0x0F)
2973
+ mac_ocp_data |= BIT_0;
2974
rtl8168_mac_ocp_write(tp, 0xE052, mac_ocp_data);
2975
rtl8168_oob_mutex_unlock(tp);
2976
2977
2978
rtl8168_eri_write(tp, 0xB8, 4, 0x00000000, ERIAR_ExGMAC);
2979
2980
rtl8168_oob_mutex_lock(tp);
2981
- rtl8168_eri_write(tp, 0x5F0, 2, 0x4000, ERIAR_ExGMAC);
2982
+ if (tp->HwPkgDet == 0x0F)
2983
+ rtl8168_eri_write(tp, 0x5F0, 2, 0x4F00, ERIAR_ExGMAC);
2984
+ else
2985
+ rtl8168_eri_write(tp, 0x5F0, 2, 0x4000, ERIAR_ExGMAC);
2986
rtl8168_oob_mutex_unlock(tp);
2987
2988
- if (tp->mcfg == CFG_METHOD_32 || tp->mcfg == CFG_METHOD_33) {
2989
+ if (tp->mcfg == CFG_METHOD_32 || tp->mcfg == CFG_METHOD_33 ||
2990
+ tp->mcfg == CFG_METHOD_34) {
2991
csi_tmp = rtl8168_eri_read(tp, 0xD4, 4, ERIAR_ExGMAC);
2992
csi_tmp |= BIT_4;
2993
rtl8168_eri_write(tp, 0xD4, 4, csi_tmp, ERIAR_ExGMAC);
2994
2995
break;
2996
case CFG_METHOD_29:
2997
case CFG_METHOD_30:
2998
+ case CFG_METHOD_35:
2999
rtl8168_mac_ocp_write(tp, 0xE098, 0x0AA2);
3000
break;
3001
case CFG_METHOD_31:
3002
case CFG_METHOD_32:
3003
case CFG_METHOD_33:
3004
+ case CFG_METHOD_34:
3005
rtl8168_mac_ocp_write(tp, 0xE098, 0xC302);
3006
break;
3007
}
3008
3009
case CFG_METHOD_31:
3010
case CFG_METHOD_32:
3011
case CFG_METHOD_33:
3012
+ case CFG_METHOD_34:
3013
+ case CFG_METHOD_35:
3014
if (aspm) {
3015
rtl8168_init_pci_offset_99(tp);
3016
}
3017
3018
case CFG_METHOD_31:
3019
case CFG_METHOD_32:
3020
case CFG_METHOD_33:
3021
+ case CFG_METHOD_34:
3022
+ case CFG_METHOD_35:
3023
if (aspm) {
3024
rtl8168_init_pci_offset_180(tp);
3025
}
3026
3027
case CFG_METHOD_30:
3028
case CFG_METHOD_31:
3029
case CFG_METHOD_32:
3030
- case CFG_METHOD_33: {
3031
+ case CFG_METHOD_33:
3032
+ case CFG_METHOD_34:
3033
+ case CFG_METHOD_35: {
3034
int timeout;
3035
for (timeout = 0; timeout < 10; timeout++) {
3036
if ((rtl8168_eri_read(tp, 0x1AE, 2, ERIAR_ExGMAC) & BIT_13)==0)
3037
3038
netif_stop_queue(dev);
3039
netif_carrier_off(dev);
3040
rtl8168_hw_config(dev);
3041
- spin_unlock_irqrestore(&tp->lock, flags);
3042
3043
rtl8168_set_speed(dev, tp->autoneg, tp->speed, tp->duplex, tp->advertising);
3044
3045
+ spin_unlock_irqrestore(&tp->lock, flags);
3046
+
3047
mod_timer(&tp->esd_timer, jiffies + RTL8168_ESD_TIMEOUT);
3048
mod_timer(&tp->link_timer, jiffies + RTL8168_LINK_TIMEOUT);
3049
out:
3050
3051
{
3052
int i;
3053
3054
- for (i = 0; i < NUM_RX_DESC; i++) {
3055
+ for (i = 0; i < tp->num_rx_desc; i++) {
3056
if (tp->Rx_skbuffi)
3057
rtl8168_free_rx_skb(tp, tp->Rx_skbuff + i,
3058
tp->RxDescArray + i);
3059
3060
u32 cur;
3061
3062
for (cur = start; end - cur > 0; cur++) {
3063
- int ret, i = cur % NUM_RX_DESC;
3064
+ int ret, i = cur % tp->num_rx_desc;
3065
3066
if (tp->Rx_skbuffi)
3067
continue;
3068
3069
{
3070
int i = 0;
3071
3072
- memset(tp->TxDescArray, 0x0, NUM_TX_DESC * sizeof(struct TxDesc));
3073
+ memset(tp->TxDescArray, 0x0, tp->num_tx_desc * sizeof(struct TxDesc));
3074
3075
- for (i = 0; i < NUM_TX_DESC; i++) {
3076
- if (i == (NUM_TX_DESC - 1))
3077
+ for (i = 0; i < tp->num_tx_desc; i++) {
3078
+ if (i == (tp->num_tx_desc - 1))
3079
tp->TxDescArrayi.opts1 = cpu_to_le32(RingEnd);
3080
}
3081
}
3082
3083
if (own)
3084
ownbit = DescOwn;
3085
3086
- for (i = 0; i < NUM_RX_DESC; i++) {
3087
- if (i == (NUM_RX_DESC - 1))
3088
+ for (i = 0; i < tp->num_rx_desc; i++) {
3089
+ if (i == (tp->num_rx_desc - 1))
3090
tp->RxDescArrayi.opts1 = cpu_to_le32((ownbit | RingEnd) | (unsigned long)tp->rx_buf_sz);
3091
else
3092
tp->RxDescArrayi.opts1 = cpu_to_le32(ownbit | (unsigned long)tp->rx_buf_sz);
3093
3094
static void
3095
rtl8168_rx_desc_init(struct rtl8168_private *tp)
3096
{
3097
- memset(tp->RxDescArray, 0x0, NUM_RX_DESC * sizeof(struct RxDesc));
3098
+ memset(tp->RxDescArray, 0x0, tp->num_rx_desc * sizeof(struct RxDesc));
3099
}
3100
3101
static int
3102
3103
3104
rtl8168_init_ring_indexes(tp);
3105
3106
- memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
3107
- memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
3108
+ memset(tp->tx_skb, 0x0, sizeof(tp->tx_skb));
3109
+ memset(tp->Rx_skbuff, 0x0, sizeof(tp->Rx_skbuff));
3110
3111
rtl8168_tx_desc_init(tp);
3112
rtl8168_rx_desc_init(tp);
3113
3114
- if (rtl8168_rx_fill(tp, dev, 0, NUM_RX_DESC, 0) != NUM_RX_DESC)
3115
+ if (rtl8168_rx_fill(tp, dev, 0, tp->num_rx_desc, 0) != tp->num_rx_desc)
3116
goto err_out;
3117
3118
- rtl8168_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
3119
+ rtl8168_mark_as_last_descriptor(tp->RxDescArray + tp->num_rx_desc - 1);
3120
3121
return 0;
3122
3123
3124
#endif
3125
3126
for (i = 0; i < n; i++) {
3127
- unsigned int entry = (start + i) % NUM_TX_DESC;
3128
+ unsigned int entry = (start + i) % tp->num_tx_desc;
3129
struct ring_info *tx_skb = tp->tx_skb + entry;
3130
unsigned int len = tx_skb->len;
3131
3132
3133
static void
3134
rtl8168_tx_clear(struct rtl8168_private *tp)
3135
{
3136
- rtl8168_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
3137
+ rtl8168_tx_clear_range(tp, tp->dirty_tx, tp->num_tx_desc);
3138
tp->cur_tx = tp->dirty_tx = 0;
3139
}
3140
3141
3142
}
3143
#endif
3144
3145
-static void
3146
-rtl8168_wait_for_quiescence(struct net_device *dev)
3147
-{
3148
- struct rtl8168_private *tp = netdev_priv(dev);
3149
-
3150
- synchronize_irq(dev->irq);
3151
-
3152
- /* Wait for any pending NAPI task to complete */
3153
-#ifdef CONFIG_R8168_NAPI
3154
-#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0)
3155
- RTL_NAPI_DISABLE(dev, &tp->napi);
3156
-#endif
3157
-#endif//CONFIG_R8168_NAPI
3158
-
3159
- rtl8168_irq_mask_and_ack(tp);
3160
-
3161
-#ifdef CONFIG_R8168_NAPI
3162
-#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0)
3163
- RTL_NAPI_ENABLE(dev, &tp->napi);
3164
-#endif
3165
-#endif//CONFIG_R8168_NAPI
3166
-}
3167
-
3168
#if 0
3169
#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
3170
static void rtl8168_reinit_task(void *_data)
3171
3172
}
3173
3174
static u32
3175
-rtl8168_get_txd_opts1(u32 opts1, u32 len, unsigned int entry)
3176
+rtl8168_get_txd_opts1(struct rtl8168_private *tp,
3177
+ u32 opts1,
3178
+ u32 len,
3179
+ unsigned int entry)
3180
{
3181
u32 status = opts1 | len;
3182
3183
- if (entry == NUM_TX_DESC - 1)
3184
+ if (entry == tp->num_tx_desc - 1)
3185
status |= RingEnd;
3186
3187
return status;
3188
3189
u32 status, len;
3190
void *addr;
3191
3192
- entry = (entry + 1) % NUM_TX_DESC;
3193
+ entry = (entry + 1) % tp->num_tx_desc;
3194
3195
txd = tp->TxDescArray + entry;
3196
#if LINUX_VERSION_CODE < KERNEL_VERSION(3,2,0)
3197
3198
}
3199
3200
/* anti gcc 2.95.3 bugware (sic) */
3201
- status = rtl8168_get_txd_opts1(opts0, len, entry);
3202
+ status = rtl8168_get_txd_opts1(tp, opts0, len, entry);
3203
if (cur_frag == (nr_frags - 1)) {
3204
tp->tx_skbentry.skb = skb;
3205
status |= LastFrag;
3206
3207
static bool rtl8168_tx_slots_avail(struct rtl8168_private *tp,
3208
unsigned int nr_frags)
3209
{
3210
- unsigned int slots_avail = tp->dirty_tx + NUM_TX_DESC - tp->cur_tx;
3211
+ unsigned int slots_avail = tp->dirty_tx + tp->num_tx_desc - tp->cur_tx;
3212
3213
/* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
3214
return slots_avail > nr_frags;
3215
3216
goto err_stop;
3217
}
3218
3219
- entry = tp->cur_tx % NUM_TX_DESC;
3220
+ entry = tp->cur_tx % tp->num_tx_desc;
3221
txd = tp->TxDescArray + entry;
3222
3223
if (unlikely(le32_to_cpu(txd->opts1) & DescOwn)) {
3224
3225
opts0 |= FirstFrag | LastFrag;
3226
}
3227
3228
- opts0 = rtl8168_get_txd_opts1(opts0, len, entry);
3229
+ opts0 = rtl8168_get_txd_opts1(tp, opts0, len, entry);
3230
mapping = dma_map_single(tp_to_dev(tp), skb->data, len, DMA_TO_DEVICE);
3231
if (unlikely(dma_mapping_error(tp_to_dev(tp), mapping))) {
3232
if (unlikely(net_ratelimit()))
3233
3234
tp->dynamic_aspm_packet_count += tx_left;
3235
3236
while (tx_left > 0) {
3237
- unsigned int entry = dirty_tx % NUM_TX_DESC;
3238
+ unsigned int entry = dirty_tx % tp->num_tx_desc;
3239
struct ring_info *tx_skb = tp->tx_skb + entry;
3240
u32 len = tx_skb->len;
3241
u32 status;
3242
3243
3244
rx_quota = RTL_RX_QUOTA(budget);
3245
cur_rx = tp->cur_rx;
3246
- entry = cur_rx % NUM_RX_DESC;
3247
+ entry = cur_rx % tp->num_rx_desc;
3248
desc = tp->RxDescArray + entry;
3249
- rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
3250
+ rx_left = tp->num_rx_desc + tp->dirty_rx - cur_rx;
3251
rx_left = rtl8168_rx_quota(rx_left, (u32)rx_quota);
3252
3253
for (; rx_left > 0; rx_left--) {
3254
3255
}
3256
3257
cur_rx++;
3258
- entry = cur_rx % NUM_RX_DESC;
3259
+ entry = cur_rx % tp->num_rx_desc;
3260
desc = tp->RxDescArray + entry;
3261
#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,37)
3262
prefetch(desc);
3263
3264
* after refill ?
3265
* - how do others driver handle this condition (Uh oh...).
3266
*/
3267
- if ((tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) && netif_msg_intr(tp))
3268
+ if ((tp->dirty_rx + tp->num_rx_desc == tp->cur_rx) && netif_msg_intr(tp))
3269
printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name);
3270
3271
rx_out:
3272
3273
case CFG_METHOD_31:
3274
case CFG_METHOD_32:
3275
case CFG_METHOD_33:
3276
+ case CFG_METHOD_34:
3277
+ case CFG_METHOD_35:
3278
/* RX_OVERFLOW RE-START mechanism now HW handles it automatically*/
3279
RTL_W16(tp, IntrStatus, status&~RxFIFOOver);
3280
break;
3281
3282
3283
if (status & tp->intr_mask)
3284
tp->keep_intr_cnt = RTK_KEEP_INTERRUPT_COUNT;
3285
+
3286
+ rtl8168_tx_interrupt(dev, tp);
3287
+
3288
#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24)
3289
rtl8168_rx_interrupt(dev, tp, &budget);
3290
#else
3291
rtl8168_rx_interrupt(dev, tp, budget);
3292
#endif //LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24)
3293
- rtl8168_tx_interrupt(dev, tp);
3294
3295
#ifdef ENABLE_DASH_SUPPORT
3296
if ( tp->DASH ) {
3297
3298
unsigned int work_done;
3299
unsigned long flags;
3300
3301
- work_done = rtl8168_rx_interrupt(dev, tp, budget);
3302
-
3303
spin_lock_irqsave(&tp->lock, flags);
3304
rtl8168_tx_interrupt(dev, tp);
3305
spin_unlock_irqrestore(&tp->lock, flags);
3306
3307
+ work_done = rtl8168_rx_interrupt(dev, tp, budget);
3308
+
3309
RTL_NAPI_QUOTA_UPDATE(dev, work_done, budget);
3310
3311
if (work_done < work_to_do) {
3312
3313
3314
free_irq(dev->irq, dev);
3315
3316
- dma_free_coherent(&pdev->dev, R8168_RX_RING_BYTES, tp->RxDescArray,
3317
+ dma_free_coherent(&pdev->dev,
3318
+ (tp->num_rx_desc * sizeof(struct RxDesc)),
3319
+ tp->RxDescArray,
3320
tp->RxPhyAddr);
3321
- dma_free_coherent(&pdev->dev, R8168_TX_RING_BYTES, tp->TxDescArray,
3322
+ dma_free_coherent(&pdev->dev,
3323
+ (tp->num_tx_desc * sizeof(struct TxDesc)),
3324
+ tp->TxDescArray,
3325
tp->TxPhyAddr);
3326
tp->TxDescArray = NULL;
3327
tp->RxDescArray = NULL;
3328
3329
rtl8168_rar_set(tp, tp->org_mac_addr);
3330
3331
#ifdef ENABLE_FIBER_SUPPORT
3332
- rtl8168_hw_fiber_nic_d3_para(dev);
3333
+ rtl8168_hw_fiber_nic_d3_para(tp);
3334
#endif //ENABLE_FIBER_SUPPORT
3335
3336
if (s5wol == 0)
3337
3338
rtl8168_hw_d3_para(dev);
3339
3340
#ifdef ENABLE_FIBER_SUPPORT
3341
- rtl8168_hw_fiber_nic_d3_para(dev);
3342
+ rtl8168_hw_fiber_nic_d3_para(tp);
3343
#endif //ENABLE_FIBER_SUPPORT
3344
3345
rtl8168_powerdown_pll(dev);
3346
r8168-8.049.02.tar.gz/src/r8168_realwow.h -> r8168-8.050.00.tar.gz/src/r8168_realwow.h
Changed
10
1
2
# r8168 is the Linux device driver released for Realtek Gigabit Ethernet
3
# controllers with PCI-Express interface.
4
#
5
-# Copyright(c) 2021 Realtek Semiconductor Corp. All rights reserved.
6
+# Copyright(c) 2022 Realtek Semiconductor Corp. All rights reserved.
7
#
8
# This program is free software; you can redistribute it and/or modify it
9
# under the terms of the GNU General Public License as published by the Free
10
r8168-8.049.02.tar.gz/src/rtl_eeprom.c -> r8168-8.050.00.tar.gz/src/rtl_eeprom.c
Changed
10
1
2
# r8168 is the Linux device driver released for Realtek Gigabit Ethernet
3
# controllers with PCI-Express interface.
4
#
5
-# Copyright(c) 2021 Realtek Semiconductor Corp. All rights reserved.
6
+# Copyright(c) 2022 Realtek Semiconductor Corp. All rights reserved.
7
#
8
# This program is free software; you can redistribute it and/or modify it
9
# under the terms of the GNU General Public License as published by the Free
10
r8168-8.049.02.tar.gz/src/rtl_eeprom.h -> r8168-8.050.00.tar.gz/src/rtl_eeprom.h
Changed
10
1
2
# r8168 is the Linux device driver released for Realtek Gigabit Ethernet
3
# controllers with PCI-Express interface.
4
#
5
-# Copyright(c) 2021 Realtek Semiconductor Corp. All rights reserved.
6
+# Copyright(c) 2022 Realtek Semiconductor Corp. All rights reserved.
7
#
8
# This program is free software; you can redistribute it and/or modify it
9
# under the terms of the GNU General Public License as published by the Free
10
r8168-8.049.02.tar.gz/src/rtltool.c -> r8168-8.050.00.tar.gz/src/rtltool.c
Changed
201
1
2
# r8168 is the Linux device driver released for Realtek Gigabit Ethernet
3
# controllers with PCI-Express interface.
4
#
5
-# Copyright(c) 2021 Realtek Semiconductor Corp. All rights reserved.
6
+# Copyright(c) 2022 Realtek Semiconductor Corp. All rights reserved.
7
#
8
# This program is free software; you can redistribute it and/or modify it
9
# under the terms of the GNU General Public License as published by the Free
10
11
ret = 0;
12
switch (my_cmd.cmd) {
13
case RTLTOOL_READ_MAC:
14
- if (!capable(CAP_NET_ADMIN))
15
- return -EPERM;
16
-
17
if (my_cmd.len==1)
18
my_cmd.data = readb(tp->mmio_addr+my_cmd.offset);
19
else if (my_cmd.len==2)
20
21
break;
22
23
case RTLTOOL_WRITE_MAC:
24
- if (!capable(CAP_NET_ADMIN))
25
- return -EPERM;
26
-
27
if (my_cmd.len==1)
28
writeb(my_cmd.data, tp->mmio_addr+my_cmd.offset);
29
else if (my_cmd.len==2)
30
31
break;
32
33
case RTLTOOL_READ_PHY:
34
- if (!capable(CAP_NET_ADMIN))
35
- return -EPERM;
36
-
37
spin_lock_irqsave(&tp->lock, flags);
38
my_cmd.data = rtl8168_mdio_prot_read(tp, my_cmd.offset);
39
spin_unlock_irqrestore(&tp->lock, flags);
40
41
break;
42
43
case RTLTOOL_WRITE_PHY:
44
- if (!capable(CAP_NET_ADMIN))
45
- return -EPERM;
46
-
47
spin_lock_irqsave(&tp->lock, flags);
48
rtl8168_mdio_prot_write(tp, my_cmd.offset, my_cmd.data);
49
spin_unlock_irqrestore(&tp->lock, flags);
50
break;
51
52
case RTLTOOL_READ_EPHY:
53
- if (!capable(CAP_NET_ADMIN))
54
- return -EPERM;
55
-
56
spin_lock_irqsave(&tp->lock, flags);
57
my_cmd.data = rtl8168_ephy_read(tp, my_cmd.offset);
58
spin_unlock_irqrestore(&tp->lock, flags);
59
60
break;
61
62
case RTLTOOL_WRITE_EPHY:
63
- if (!capable(CAP_NET_ADMIN))
64
- return -EPERM;
65
-
66
spin_lock_irqsave(&tp->lock, flags);
67
rtl8168_ephy_write(tp, my_cmd.offset, my_cmd.data);
68
spin_unlock_irqrestore(&tp->lock, flags);
69
70
break;
71
72
case RTLTOOL_WRITE_ERI:
73
- if (!capable(CAP_NET_ADMIN))
74
- return -EPERM;
75
-
76
- if (!capable(CAP_NET_ADMIN))
77
- return -EPERM;
78
-
79
if (my_cmd.len==1 || my_cmd.len==2 || my_cmd.len==4) {
80
spin_lock_irqsave(&tp->lock, flags);
81
rtl8168_eri_write(tp, my_cmd.offset, my_cmd.len, my_cmd.data, ERIAR_ExGMAC);
82
83
break;
84
85
case RTLTOOL_READ_PCI:
86
- if (!capable(CAP_NET_ADMIN))
87
- return -EPERM;
88
-
89
my_cmd.data = 0;
90
if (my_cmd.len==1)
91
pci_read_config_byte(tp->pci_dev, my_cmd.offset,
92
93
break;
94
95
case RTLTOOL_WRITE_PCI:
96
- if (!capable(CAP_NET_ADMIN))
97
- return -EPERM;
98
-
99
if (my_cmd.len==1)
100
pci_write_config_byte(tp->pci_dev, my_cmd.offset,
101
my_cmd.data);
102
103
break;
104
105
case RTLTOOL_READ_EEPROM:
106
- if (!capable(CAP_NET_ADMIN))
107
- return -EPERM;
108
-
109
spin_lock_irqsave(&tp->lock, flags);
110
my_cmd.data = rtl8168_eeprom_read_sc(tp, my_cmd.offset);
111
spin_unlock_irqrestore(&tp->lock, flags);
112
113
break;
114
115
case RTLTOOL_WRITE_EEPROM:
116
- if (!capable(CAP_NET_ADMIN))
117
- return -EPERM;
118
-
119
spin_lock_irqsave(&tp->lock, flags);
120
rtl8168_eeprom_write_sc(tp, my_cmd.offset, my_cmd.data);
121
spin_unlock_irqrestore(&tp->lock, flags);
122
break;
123
124
case RTL_READ_OOB_MAC:
125
- if (!capable(CAP_NET_ADMIN))
126
- return -EPERM;
127
-
128
spin_lock_irqsave(&tp->lock, flags);
129
rtl8168_oob_mutex_lock(tp);
130
my_cmd.data = rtl8168_ocp_read(tp, my_cmd.offset, 4);
131
132
break;
133
134
case RTL_WRITE_OOB_MAC:
135
- if (!capable(CAP_NET_ADMIN))
136
- return -EPERM;
137
-
138
if (my_cmd.len == 0 || my_cmd.len > 4)
139
return -EOPNOTSUPP;
140
141
142
break;
143
144
case RTL_ENABLE_PCI_DIAG:
145
- if (!capable(CAP_NET_ADMIN))
146
- return -EPERM;
147
-
148
spin_lock_irqsave(&tp->lock, flags);
149
tp->rtk_enable_diag = 1;
150
spin_unlock_irqrestore(&tp->lock, flags);
151
152
break;
153
154
case RTL_DISABLE_PCI_DIAG:
155
- if (!capable(CAP_NET_ADMIN))
156
- return -EPERM;
157
-
158
spin_lock_irqsave(&tp->lock, flags);
159
tp->rtk_enable_diag = 0;
160
spin_unlock_irqrestore(&tp->lock, flags);
161
162
break;
163
164
case RTL_READ_MAC_OCP:
165
- if (!capable(CAP_NET_ADMIN))
166
- return -EPERM;
167
-
168
if (my_cmd.offset % 2)
169
return -EOPNOTSUPP;
170
171
172
break;
173
174
case RTL_WRITE_MAC_OCP:
175
- if (!capable(CAP_NET_ADMIN))
176
- return -EPERM;
177
-
178
if ((my_cmd.offset % 2) || (my_cmd.len != 2))
179
return -EOPNOTSUPP;
180
181
182
break;
183
184
case RTL_DIRECT_READ_PHY_OCP:
185
- if (!capable(CAP_NET_ADMIN))
186
- return -EPERM;
187
-
188
spin_lock_irqsave(&tp->lock, flags);
189
my_cmd.data = rtl8168_mdio_prot_direct_read_phy_ocp(tp, my_cmd.offset);
190
spin_unlock_irqrestore(&tp->lock, flags);
191
192
break;
193
194
case RTL_DIRECT_WRITE_PHY_OCP:
195
- if (!capable(CAP_NET_ADMIN))
196
- return -EPERM;
197
-
198
spin_lock_irqsave(&tp->lock, flags);
199
rtl8168_mdio_prot_direct_write_phy_ocp(tp, my_cmd.offset, my_cmd.data);
200
spin_unlock_irqrestore(&tp->lock, flags);
201
r8168-8.049.02.tar.gz/src/rtltool.h -> r8168-8.050.00.tar.gz/src/rtltool.h
Changed
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# r8168 is the Linux device driver released for Realtek Gigabit Ethernet
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# controllers with PCI-Express interface.
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#
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-# Copyright(c) 2021 Realtek Semiconductor Corp. All rights reserved.
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+# Copyright(c) 2022 Realtek Semiconductor Corp. All rights reserved.
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#
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# This program is free software; you can redistribute it and/or modify it
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# under the terms of the GNU General Public License as published by the Free
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Request History
bitstreamout created request almost 3 years ago
- Update to new version 8.050.00
- Port patches r8168-kernel_version.patch and r8168-configuration.patch
bitstreamout accepted request almost 3 years ago
Let's try