Overview

Request 4992 (accepted)

- Update to new version 8.048.00
- Modify patch r8168-kernel_version.patch as upstream now supports 5.4

- Modify patch r8168-kernel_version.patch to let it build with 5.4

Submit package home:bitstreamout:Essentials / r8168 to package Essentials / r8168

r8168.changes Changed
x
 
1
@@ -1,8 +1,14 @@
2
 -------------------------------------------------------------------
3
+Mon Feb 10 11:38:00 UTC 2020 - Werner Fink <werner@suse.de>
4
+
5
+- Update to new version 8.048.00 
6
+- Modify patch r8168-kernel_version.patch as upstream now supports 5.4
7
+
8
+-------------------------------------------------------------------
9
 Tue Nov 26 10:08:11 UTC 2019 - Werner Fink <werner@suse.de>
10
 
11
 - Update to new version 8.047.05
12
-- Motify patch r8168-kernel_version.patch to let it build with 5.4
13
+- Modify patch r8168-kernel_version.patch to let it build with 5.4
14
 
15
 -------------------------------------------------------------------
16
 Thu Oct 24 05:49:20 UTC 2019 - Werner Fink <werner@suse.de>
17
r8168.spec Changed
10
 
1
@@ -18,7 +18,7 @@
2
 
3
 #!BuildIgnore: enough-build-resources
4
 Name:           r8168
5
-Version:        8.047.05
6
+Version:        8.048.00
7
 Release:        0
8
 Summary:        Device driver for RealTek Gigabit Ethernet controllers
9
 License:        GPL-2.0-or-later
10
r8168-kernel_version.patch Changed
35
 
1
@@ -1,10 +1,10 @@
2
 ---
3
  src/r8168.h   |    4 ++++
4
- src/r8168_n.c |    4 ++--
5
- 2 files changed, 6 insertions(+), 2 deletions(-)
6
+ src/r8168_n.c |    2 +-
7
+ 2 files changed, 5 insertions(+), 1 deletion(-)
8
 
9
 --- src/r8168.h
10
-+++ src/r8168.h    2019-11-26 10:20:59.180216676 +0000
11
++++ src/r8168.h    2020-02-10 11:32:37.788832833 +0000
12
 @@ -116,6 +116,10 @@ do { \
13
  } while (0)
14
  #endif //LINUX_VERSION_CODE < KERNEL_VERSION(2,6,15)
15
@@ -17,17 +17,8 @@
16
  #if defined(skb_vlan_tag_present) && !defined(vlan_tx_tag_present)
17
  #define vlan_tx_tag_present skb_vlan_tag_present
18
 --- src/r8168_n.c
19
-+++ src/r8168_n.c  2019-11-26 10:22:05.270987378 +0000
20
-@@ -56,7 +56,7 @@
21
- #include <linux/rtnetlink.h>
22
- #include <linux/completion.h>
23
- 
24
--#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26)
25
-+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26)) && (LINUX_VERSION_CODE < KERNEL_VERSION(5,4,0))
26
- #include <linux/pci-aspm.h>
27
- #endif
28
- #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,37)
29
-@@ -28476,7 +28476,7 @@ process_pkt:
30
++++ src/r8168_n.c  2020-02-10 11:32:37.788832833 +0000
31
+@@ -28535,7 +28535,7 @@ process_pkt:
32
  
33
                          if (rtl8168_rx_vlan_skb(tp, desc, skb) < 0)
34
                                  rtl8168_rx_skb(tp, skb);
35
r8168-8.047.05.tar.bz2/src/Makefile -> r8168-8.048.00.tar.bz2/src/Makefile Changed
10
 
1
@@ -38,7 +38,7 @@
2
 CONFIG_ASPM = y
3
 ENABLE_S5WOL = y
4
 ENABLE_S5_KEEP_CURR_MAC = n
5
-ENABLE_EEE = n
6
+ENABLE_EEE = y
7
 ENABLE_S0_MAGIC_PACKET = n
8
 
9
 ifneq ($(KERNELRELEASE),)
10
r8168-8.047.05.tar.bz2/src/r8168.h -> r8168-8.048.00.tar.bz2/src/r8168.h Changed
92
 
1
@@ -250,6 +250,14 @@
2
 #define SUPPORTED_Asym_Pause  (1 << 14)
3
 #endif
4
 
5
+#ifndef  MDIO_EEE_100TX
6
+#define  MDIO_EEE_100TX  0x0002
7
+#endif
8
+
9
+#ifndef  MDIO_EEE_1000T
10
+#define  MDIO_EEE_1000T  0x0004
11
+#endif
12
+
13
 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,29)
14
 #ifdef CONFIG_NET_POLL_CONTROLLER
15
 #define RTL_NET_POLL_CONTROLLER dev->poll_controller=rtl8168_netpoll
16
@@ -327,7 +335,7 @@
17
 #define DASH_SUFFIX ""
18
 #endif
19
 
20
-#define RTL8168_VERSION "8.047.05" NAPI_SUFFIX FIBER_SUFFIX REALWOW_SUFFIX DASH_SUFFIX
21
+#define RTL8168_VERSION "8.048.00" NAPI_SUFFIX FIBER_SUFFIX REALWOW_SUFFIX DASH_SUFFIX
22
 #define MODULENAME "r8168"
23
 #define PFX MODULENAME ": "
24
 
25
@@ -430,12 +438,12 @@
26
 #define SHORT_PACKET_PADDING_BUF_SIZE 256
27
 
28
 /* write/read MMIO register */
29
-#define RTL_W8(reg, val8)   writeb ((val8), ioaddr + (reg))
30
-#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
31
-#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
32
-#define RTL_R8(reg)     readb (ioaddr + (reg))
33
-#define RTL_R16(reg)        readw (ioaddr + (reg))
34
-#define RTL_R32(reg)        ((unsigned long) readl (ioaddr + (reg)))
35
+#define RTL_W8(tp, reg, val8)  writeb((val8), tp->mmio_addr + (reg))
36
+#define RTL_W16(tp, reg, val16)    writew((val16), tp->mmio_addr + (reg))
37
+#define RTL_W32(tp, reg, val32)    writel((val32), tp->mmio_addr + (reg))
38
+#define RTL_R8(tp, reg)        readb(tp->mmio_addr + (reg))
39
+#define RTL_R16(tp, reg)       readw(tp->mmio_addr + (reg))
40
+#define RTL_R32(tp, reg)       ((unsigned long) readl(tp->mmio_addr + (reg)))
41
 
42
 #ifndef DMA_64BIT_MASK
43
 #define DMA_64BIT_MASK  0xffffffffffffffffULL
44
@@ -1564,6 +1572,8 @@
45
         u32 HwFiberStat;
46
         u8 HwSwitchMdiToFiber;
47
 
48
+        u8 HwSuppPhyOcpVer;
49
+
50
         u16 NicCustLedValue;
51
 
52
         u8 HwSuppMagicPktVer;
53
@@ -1716,6 +1726,7 @@
54
         CFG_METHOD_30,
55
         CFG_METHOD_31,
56
         CFG_METHOD_32,
57
+        CFG_METHOD_33,
58
         CFG_METHOD_MAX,
59
         CFG_METHOD_DEFAULT = 0xFF
60
 };
61
@@ -1767,7 +1778,7 @@
62
 u32 rtl8168_mdio_read(struct rtl8168_private *tp, u32 RegAddr);
63
 u32 rtl8168_mdio_prot_read(struct rtl8168_private *tp, u32 RegAddr);
64
 u32 rtl8168_mdio_prot_direct_read_phy_ocp(struct rtl8168_private *tp, u32 RegAddr);
65
-void rtl8168_ephy_write(void __iomem *ioaddr, int RegAddr, int value);
66
+void rtl8168_ephy_write(struct rtl8168_private *tp, int RegAddr, int value);
67
 void rtl8168_mac_ocp_write(struct rtl8168_private *tp, u16 reg_addr, u16 value);
68
 u16 rtl8168_mac_ocp_read(struct rtl8168_private *tp, u16 reg_addr);
69
 void rtl8168_clear_eth_phy_bit(struct rtl8168_private *tp, u8 addr, u16 mask);
70
@@ -1775,16 +1786,16 @@
71
 void rtl8168_ocp_write(struct rtl8168_private *tp, u16 addr, u8 len, u32 data);
72
 void rtl8168_oob_notify(struct rtl8168_private *tp, u8 cmd);
73
 void rtl8168_init_ring_indexes(struct rtl8168_private *tp);
74
-int rtl8168_eri_write(void __iomem *ioaddr, int addr, int len, u32 value, int type);
75
+int rtl8168_eri_write(struct rtl8168_private *tp, int addr, int len, u32 value, int type);
76
 void rtl8168_oob_mutex_lock(struct rtl8168_private *tp);
77
 u32 rtl8168_mdio_read(struct rtl8168_private *tp, u32 RegAddr);
78
 u32 rtl8168_ocp_read(struct rtl8168_private *tp, u16 addr, u8 len);
79
 u32 rtl8168_ocp_read_with_oob_base_address(struct rtl8168_private *tp, u16 addr, u8 len, u32 base_address);
80
 u32 rtl8168_ocp_write_with_oob_base_address(struct rtl8168_private *tp, u16 addr, u8 len, u32 value, u32 base_address);
81
-u32 rtl8168_eri_read(void __iomem *ioaddr, int addr, int len, int type);
82
-u32 rtl8168_eri_read_with_oob_base_address(void __iomem *ioaddr, int addr, int len, int type, u32 base_address);
83
-int rtl8168_eri_write_with_oob_base_address(void __iomem *ioaddr, int addr, int len, u32 value, int type, u32 base_address);
84
-u16 rtl8168_ephy_read(void __iomem *ioaddr, int RegAddr);
85
+u32 rtl8168_eri_read(struct rtl8168_private *tp, int addr, int len, int type);
86
+u32 rtl8168_eri_read_with_oob_base_address(struct rtl8168_private *tp, int addr, int len, int type, u32 base_address);
87
+int rtl8168_eri_write_with_oob_base_address(struct rtl8168_private *tp, int addr, int len, u32 value, int type, u32 base_address);
88
+u16 rtl8168_ephy_read(struct rtl8168_private *tp, int RegAddr);
89
 void rtl8168_wait_txrx_fifo_empty(struct net_device *dev);
90
 void rtl8168_wait_ll_share_fifo_ready(struct net_device *dev);
91
 void rtl8168_enable_now_is_oob(struct rtl8168_private *tp);
92
r8168-8.047.05.tar.bz2/src/r8168_asf.c -> r8168-8.048.00.tar.bz2/src/r8168_asf.c Changed
399
 
1
@@ -57,7 +57,6 @@
2
                       struct ifreq *ifr)
3
 {
4
         struct rtl8168_private *tp = netdev_priv(dev);
5
-        void __iomem *ioaddr = tp->mmio_addr;
6
         void *user_data = ifr->ifr_data;
7
         struct asf_ioctl_struct asf_usrdata;
8
         unsigned long flags;
9
@@ -72,126 +71,127 @@
10
 
11
         switch (asf_usrdata.offset) {
12
         case HBPeriod:
13
-                rtl8168_asf_hbperiod(ioaddr, asf_usrdata.arg, asf_usrdata.u.data);
14
+                rtl8168_asf_hbperiod(tp, asf_usrdata.arg, asf_usrdata.u.data);
15
                 break;
16
         case WD8Timer:
17
                 break;
18
         case WD16Rst:
19
-                rtl8168_asf_wd16rst(ioaddr, asf_usrdata.arg, asf_usrdata.u.data);
20
+                rtl8168_asf_wd16rst(tp, asf_usrdata.arg, asf_usrdata.u.data);
21
                 break;
22
         case WD8Rst:
23
-                rtl8168_asf_time_period(ioaddr, asf_usrdata.arg, WD8Rst, asf_usrdata.u.data);
24
+                rtl8168_asf_time_period(tp, asf_usrdata.arg, WD8Rst, asf_usrdata.u.data);
25
                 break;
26
         case LSnsrPollCycle:
27
-                rtl8168_asf_time_period(ioaddr, asf_usrdata.arg, LSnsrPollCycle, asf_usrdata.u.data);
28
+                rtl8168_asf_time_period(tp, asf_usrdata.arg, LSnsrPollCycle, asf_usrdata.u.data);
29
                 break;
30
         case ASFSnsrPollPrd:
31
-                rtl8168_asf_time_period(ioaddr, asf_usrdata.arg, ASFSnsrPollPrd, asf_usrdata.u.data);
32
+                rtl8168_asf_time_period(tp, asf_usrdata.arg, ASFSnsrPollPrd, asf_usrdata.u.data);
33
                 break;
34
         case AlertReSendItvl:
35
-                rtl8168_asf_time_period(ioaddr, asf_usrdata.arg, AlertReSendItvl, asf_usrdata.u.data);
36
+                rtl8168_asf_time_period(tp, asf_usrdata.arg, AlertReSendItvl, asf_usrdata.u.data);
37
                 break;
38
         case SMBAddr:
39
-                rtl8168_asf_rw_hexadecimal(ioaddr, asf_usrdata.arg, SMBAddr, RW_ONE_BYTE, asf_usrdata.u.data);
40
+                rtl8168_asf_rw_hexadecimal(tp, asf_usrdata.arg, SMBAddr, RW_ONE_BYTE, asf_usrdata.u.data);
41
                 break;
42
         case ASFConfigR0:
43
-                rtl8168_asf_config_regs(ioaddr, asf_usrdata.arg, ASFConfigR0, asf_usrdata.u.data);
44
+                rtl8168_asf_config_regs(tp, asf_usrdata.arg, ASFConfigR0, asf_usrdata.u.data);
45
                 break;
46
         case ASFConfigR1:
47
-                rtl8168_asf_config_regs(ioaddr, asf_usrdata.arg, ASFConfigR1, asf_usrdata.u.data);
48
+                rtl8168_asf_config_regs(tp, asf_usrdata.arg, ASFConfigR1, asf_usrdata.u.data);
49
                 break;
50
         case ConsoleMA:
51
                 rtl8168_asf_console_mac(tp, asf_usrdata.arg, asf_usrdata.u.data);
52
                 break;
53
         case ConsoleIP:
54
-                rtl8168_asf_ip_address(ioaddr, asf_usrdata.arg, ConsoleIP, asf_usrdata.u.data);
55
+                rtl8168_asf_ip_address(tp, asf_usrdata.arg, ConsoleIP, asf_usrdata.u.data);
56
                 break;
57
         case IPAddr:
58
                 rtl8168_asf_ip_address(tp, asf_usrdata.arg, IPAddr, asf_usrdata.u.data);
59
                 break;
60
         case UUID:
61
-                rtl8168_asf_rw_uuid(ioaddr, asf_usrdata.arg, asf_usrdata.u.data);
62
+                rtl8168_asf_rw_uuid(tp, asf_usrdata.arg, asf_usrdata.u.data);
63
                 break;
64
         case IANA:
65
-                rtl8168_asf_rw_iana(ioaddr, asf_usrdata.arg, asf_usrdata.u.data);
66
+                rtl8168_asf_rw_iana(tp, asf_usrdata.arg, asf_usrdata.u.data);
67
                 break;
68
         case SysID:
69
-                rtl8168_asf_rw_systemid(ioaddr, asf_usrdata.arg, asf_usrdata.u.data);
70
+                rtl8168_asf_rw_systemid(tp, asf_usrdata.arg, asf_usrdata.u.data);
71
                 break;
72
         case Community:
73
-                rtl8168_asf_community_string(ioaddr, asf_usrdata.arg, asf_usrdata.u.string);
74
+                rtl8168_asf_community_string(tp, asf_usrdata.arg, asf_usrdata.u.string);
75
                 break;
76
         case StringLength:
77
-                rtl8168_asf_community_string_len(ioaddr, asf_usrdata.arg, asf_usrdata.u.data);
78
+                rtl8168_asf_community_string_len(tp, asf_usrdata.arg, asf_usrdata.u.data);
79
                 break;
80
         case FmCapMsk:
81
-                rtl8168_asf_capability_masks(ioaddr, asf_usrdata.arg, FmCapMsk, asf_usrdata.u.data);
82
+                rtl8168_asf_capability_masks(tp, asf_usrdata.arg, FmCapMsk, asf_usrdata.u.data);
83
                 break;
84
         case SpCMDMsk:
85
-                rtl8168_asf_capability_masks(ioaddr, asf_usrdata.arg, SpCMDMsk, asf_usrdata.u.data);
86
+                rtl8168_asf_capability_masks(tp, asf_usrdata.arg, SpCMDMsk, asf_usrdata.u.data);
87
                 break;
88
         case SysCapMsk:
89
-                rtl8168_asf_capability_masks(ioaddr, asf_usrdata.arg, SysCapMsk, asf_usrdata.u.data);
90
+                rtl8168_asf_capability_masks(tp, asf_usrdata.arg, SysCapMsk, asf_usrdata.u.data);
91
                 break;
92
         case RmtRstAddr:
93
-                rtl8168_asf_rw_hexadecimal(ioaddr, asf_usrdata.arg, RmtRstAddr, RW_ONE_BYTE, asf_usrdata.u.data);
94
+                rtl8168_asf_rw_hexadecimal(tp, asf_usrdata.arg, RmtRstAddr, RW_ONE_BYTE, asf_usrdata.u.data);
95
                 break;
96
         case RmtRstCmd:
97
-                rtl8168_asf_rw_hexadecimal(ioaddr, asf_usrdata.arg, RmtRstCmd, RW_ONE_BYTE, asf_usrdata.u.data);
98
+                rtl8168_asf_rw_hexadecimal(tp, asf_usrdata.arg, RmtRstCmd, RW_ONE_BYTE, asf_usrdata.u.data);
99
                 break;
100
         case RmtRstData:
101
-                rtl8168_asf_rw_hexadecimal(ioaddr, asf_usrdata.arg, RmtRstData, RW_ONE_BYTE, asf_usrdata.u.data);
102
+                rtl8168_asf_rw_hexadecimal(tp, asf_usrdata.arg, RmtRstData, RW_ONE_BYTE, asf_usrdata.u.data);
103
                 break;
104
         case RmtPwrOffAddr:
105
-                rtl8168_asf_rw_hexadecimal(ioaddr, asf_usrdata.arg, RmtPwrOffAddr, RW_ONE_BYTE, asf_usrdata.u.data);
106
+                rtl8168_asf_rw_hexadecimal(tp, asf_usrdata.arg, RmtPwrOffAddr, RW_ONE_BYTE, asf_usrdata.u.data);
107
                 break;
108
         case RmtPwrOffCmd:
109
-                rtl8168_asf_rw_hexadecimal(ioaddr, asf_usrdata.arg, RmtPwrOffCmd, RW_ONE_BYTE, asf_usrdata.u.data);
110
+                rtl8168_asf_rw_hexadecimal(tp, asf_usrdata.arg, RmtPwrOffCmd, RW_ONE_BYTE, asf_usrdata.u.data);
111
                 break;
112
         case RmtPwrOffData:
113
-                rtl8168_asf_rw_hexadecimal(ioaddr, asf_usrdata.arg, RmtPwrOffData, RW_ONE_BYTE, asf_usrdata.u.data);
114
+                rtl8168_asf_rw_hexadecimal(tp, asf_usrdata.arg, RmtPwrOffData, RW_ONE_BYTE, asf_usrdata.u.data);
115
                 break;
116
         case RmtPwrOnAddr:
117
-                rtl8168_asf_rw_hexadecimal(ioaddr, asf_usrdata.arg, RmtPwrOnAddr, RW_ONE_BYTE, asf_usrdata.u.data);
118
+                rtl8168_asf_rw_hexadecimal(tp, asf_usrdata.arg, RmtPwrOnAddr, RW_ONE_BYTE, asf_usrdata.u.data);
119
                 break;
120
         case RmtPwrOnCmd:
121
-                rtl8168_asf_rw_hexadecimal(ioaddr, asf_usrdata.arg, RmtPwrOnCmd, RW_ONE_BYTE, asf_usrdata.u.data);
122
+                rtl8168_asf_rw_hexadecimal(tp, asf_usrdata.arg, RmtPwrOnCmd, RW_ONE_BYTE, asf_usrdata.u.data);
123
                 break;
124
         case RmtPwrOnData:
125
-                rtl8168_asf_rw_hexadecimal(ioaddr, asf_usrdata.arg, RmtPwrOnData, RW_ONE_BYTE, asf_usrdata.u.data);
126
+                rtl8168_asf_rw_hexadecimal(tp, asf_usrdata.arg, RmtPwrOnData, RW_ONE_BYTE, asf_usrdata.u.data);
127
                 break;
128
         case RmtPCRAddr:
129
-                rtl8168_asf_rw_hexadecimal(ioaddr, asf_usrdata.arg, RmtPCRAddr, RW_ONE_BYTE, asf_usrdata.u.data);
130
+                rtl8168_asf_rw_hexadecimal(tp, asf_usrdata.arg, RmtPCRAddr, RW_ONE_BYTE, asf_usrdata.u.data);
131
                 break;
132
         case RmtPCRCmd:
133
-                rtl8168_asf_rw_hexadecimal(ioaddr, asf_usrdata.arg, RmtPCRCmd, RW_ONE_BYTE, asf_usrdata.u.data);
134
+                rtl8168_asf_rw_hexadecimal(tp, asf_usrdata.arg, RmtPCRCmd, RW_ONE_BYTE, asf_usrdata.u.data);
135
                 break;
136
         case RmtPCRData:
137
-                rtl8168_asf_rw_hexadecimal(ioaddr, asf_usrdata.arg, RmtPCRData, RW_ONE_BYTE, asf_usrdata.u.data);
138
+                rtl8168_asf_rw_hexadecimal(tp, asf_usrdata.arg, RmtPCRData, RW_ONE_BYTE, asf_usrdata.u.data);
139
                 break;
140
         case ASFSnsr0Addr:
141
-                rtl8168_asf_rw_hexadecimal(ioaddr, asf_usrdata.arg, ASFSnsr0Addr, RW_ONE_BYTE, asf_usrdata.u.data);
142
+                rtl8168_asf_rw_hexadecimal(tp, asf_usrdata.arg, ASFSnsr0Addr, RW_ONE_BYTE, asf_usrdata.u.data);
143
                 break;
144
         case LSnsrAddr0:
145
-                rtl8168_asf_rw_hexadecimal(ioaddr, asf_usrdata.arg, LSnsrAddr0, RW_ONE_BYTE, asf_usrdata.u.data);
146
+                rtl8168_asf_rw_hexadecimal(tp, asf_usrdata.arg, LSnsrAddr0, RW_ONE_BYTE, asf_usrdata.u.data);
147
                 break;
148
         case KO:
149
                 /* Get/Set Key Operation */
150
-                rtl8168_asf_key_access(ioaddr, asf_usrdata.arg, KO, asf_usrdata.u.data);
151
+                rtl8168_asf_key_access(tp, asf_usrdata.arg, KO, asf_usrdata.u.data);
152
                 break;
153
         case KA:
154
                 /* Get/Set Key Administrator */
155
-                rtl8168_asf_key_access(ioaddr, asf_usrdata.arg, KA, asf_usrdata.u.data);
156
+                rtl8168_asf_key_access(tp, asf_usrdata.arg, KA, asf_usrdata.u.data);
157
                 break;
158
         case KG:
159
                 /* Get/Set Key Generation */
160
-                rtl8168_asf_key_access(ioaddr, asf_usrdata.arg, KG, asf_usrdata.u.data);
161
+                rtl8168_asf_key_access(tp, asf_usrdata.arg, KG, asf_usrdata.u.data);
162
                 break;
163
         case KR:
164
                 /* Get/Set Key Random */
165
                 rtl8168_asf_key_access(tp, asf_usrdata.arg, KR, asf_usrdata.u.data);
166
                 break;
167
         default:
168
+                spin_unlock_irqrestore(&tp->lock, flags);
169
                 return -EOPNOTSUPP;
170
         }
171
 
172
@@ -203,32 +203,31 @@
173
         return 0;
174
 }
175
 
176
-void rtl8168_asf_hbperiod(void __iomem *ioaddr, int arg, unsigned int *data)
177
+void rtl8168_asf_hbperiod(struct rtl8168_private *tp, int arg, unsigned int *data)
178
 {
179
         if (arg == ASF_GET)
180
-                data[ASFHBPERIOD] = rtl8168_eri_read(ioaddr, HBPeriod, RW_TWO_BYTES, ERIAR_ASF);
181
+                data[ASFHBPERIOD] = rtl8168_eri_read(tp, HBPeriod, RW_TWO_BYTES, ERIAR_ASF);
182
         else if (arg == ASF_SET) {
183
-                rtl8168_eri_write(ioaddr, HBPeriod, RW_TWO_BYTES, data[ASFHBPERIOD], ERIAR_ASF);
184
-                rtl8168_eri_write(ioaddr, 0x1EC, RW_ONE_BYTE, 0x07, ERIAR_ASF);
185
+                rtl8168_eri_write(tp, HBPeriod, RW_TWO_BYTES, data[ASFHBPERIOD], ERIAR_ASF);
186
+                rtl8168_eri_write(tp, 0x1EC, RW_ONE_BYTE, 0x07, ERIAR_ASF);
187
         }
188
 }
189
 
190
-void rtl8168_asf_wd16rst(void __iomem *ioaddr, int arg, unsigned int *data)
191
+void rtl8168_asf_wd16rst(struct rtl8168_private *tp, int arg, unsigned int *data)
192
 {
193
-        data[ASFWD16RST] = rtl8168_eri_read(ioaddr, WD16Rst, RW_TWO_BYTES, ERIAR_ASF);
194
+        data[ASFWD16RST] = rtl8168_eri_read(tp, WD16Rst, RW_TWO_BYTES, ERIAR_ASF);
195
 }
196
 
197
 void rtl8168_asf_console_mac(struct rtl8168_private *tp, int arg, unsigned int *data)
198
 {
199
-        void __iomem *ioaddr=tp->mmio_addr;
200
         int i;
201
 
202
         if (arg == ASF_GET) {
203
                 for (i = 0; i < 6; i++)
204
-                        data[i] = rtl8168_eri_read(ioaddr, ConsoleMA + i, RW_ONE_BYTE, ERIAR_ASF);
205
+                        data[i] = rtl8168_eri_read(tp, ConsoleMA + i, RW_ONE_BYTE, ERIAR_ASF);
206
         } else if (arg == ASF_SET) {
207
                 for (i = 0; i < 6; i++)
208
-                        rtl8168_eri_write(ioaddr, ConsoleMA + i, RW_ONE_BYTE, data[i], ERIAR_ASF);
209
+                        rtl8168_eri_write(tp, ConsoleMA + i, RW_ONE_BYTE, data[i], ERIAR_ASF);
210
 
211
                 /* write the new console MAC address to EEPROM */
212
                 rtl8168_eeprom_write_sc(tp, 70, (data[1] << 8) | data[0]);
213
@@ -239,16 +238,15 @@
214
 
215
 void rtl8168_asf_ip_address(struct rtl8168_private *tp, int arg, int offset, unsigned int *data)
216
 {
217
-        void __iomem *ioaddr=tp->mmio_addr;
218
         int i;
219
         int eeprom_off = 0;
220
 
221
         if (arg == ASF_GET) {
222
                 for (i = 0; i < 4; i++)
223
-                        data[i] = rtl8168_eri_read(ioaddr, offset + i, RW_ONE_BYTE, ERIAR_ASF);
224
+                        data[i] = rtl8168_eri_read(tp, offset + i, RW_ONE_BYTE, ERIAR_ASF);
225
         } else if (arg == ASF_SET) {
226
                 for (i = 0; i < 4; i++)
227
-                        rtl8168_eri_write(ioaddr, offset + i, RW_ONE_BYTE, data[i], ERIAR_ASF);
228
+                        rtl8168_eri_write(tp, offset + i, RW_ONE_BYTE, data[i], ERIAR_ASF);
229
 
230
                 if (offset == ConsoleIP)
231
                         eeprom_off = 73;
232
@@ -262,25 +260,25 @@
233
         }
234
 }
235
 
236
-void rtl8168_asf_config_regs(void __iomem *ioaddr, int arg, int offset, unsigned int *data)
237
+void rtl8168_asf_config_regs(struct rtl8168_private *tp, int arg, int offset, unsigned int *data)
238
 {
239
         unsigned int value;
240
 
241
         if (arg == ASF_GET) {
242
-                data[ASFCAPABILITY] = (rtl8168_eri_read(ioaddr, offset, RW_ONE_BYTE, ERIAR_ASF) & data[ASFCONFIG]) ? FUNCTION_ENABLE : FUNCTION_DISABLE;
243
+                data[ASFCAPABILITY] = (rtl8168_eri_read(tp, offset, RW_ONE_BYTE, ERIAR_ASF) & data[ASFCONFIG]) ? FUNCTION_ENABLE : FUNCTION_DISABLE;
244
         } else if (arg == ASF_SET) {
245
-                value = rtl8168_eri_read(ioaddr, offset, RW_ONE_BYTE, ERIAR_ASF);
246
+                value = rtl8168_eri_read(tp, offset, RW_ONE_BYTE, ERIAR_ASF);
247
 
248
                 if (data[ASFCAPABILITY] == FUNCTION_ENABLE)
249
                         value |= data[ASFCONFIG];
250
                 else if (data[ASFCAPABILITY] == FUNCTION_DISABLE)
251
                         value &= ~data[ASFCONFIG];
252
 
253
-                rtl8168_eri_write(ioaddr, offset, RW_ONE_BYTE, value, ERIAR_ASF);
254
+                rtl8168_eri_write(tp, offset, RW_ONE_BYTE, value, ERIAR_ASF);
255
         }
256
 }
257
 
258
-void rtl8168_asf_capability_masks(void __iomem *ioaddr, int arg, int offset, unsigned int *data)
259
+void rtl8168_asf_capability_masks(struct rtl8168_private *tp, int arg, int offset, unsigned int *data)
260
 {
261
         unsigned int len, bit_mask;
262
 
263
@@ -304,33 +302,33 @@
264
         }
265
 
266
         if (arg == ASF_GET)
267
-                data[ASFCAPMASK] = rtl8168_eri_read(ioaddr, offset, len, ERIAR_ASF) ? FUNCTION_ENABLE : FUNCTION_DISABLE;
268
+                data[ASFCAPMASK] = rtl8168_eri_read(tp, offset, len, ERIAR_ASF) ? FUNCTION_ENABLE : FUNCTION_DISABLE;
269
         else /* arg == ASF_SET */
270
-                rtl8168_eri_write(ioaddr, offset, len, bit_mask, ERIAR_ASF);
271
+                rtl8168_eri_write(tp, offset, len, bit_mask, ERIAR_ASF);
272
 }
273
 
274
-void rtl8168_asf_community_string(void __iomem *ioaddr, int arg, char *string)
275
+void rtl8168_asf_community_string(struct rtl8168_private *tp, int arg, char *string)
276
 {
277
         int i;
278
 
279
         if (arg == ASF_GET) {
280
                 for (i = 0; i < COMMU_STR_MAX_LEN; i++)
281
-                        string[i] = rtl8168_eri_read(ioaddr, Community + i, RW_ONE_BYTE, ERIAR_ASF);
282
+                        string[i] = rtl8168_eri_read(tp, Community + i, RW_ONE_BYTE, ERIAR_ASF);
283
         } else { /* arg == ASF_SET */
284
                 for (i = 0; i < COMMU_STR_MAX_LEN; i++)
285
-                        rtl8168_eri_write(ioaddr, Community + i, RW_ONE_BYTE, string[i], ERIAR_ASF);
286
+                        rtl8168_eri_write(tp, Community + i, RW_ONE_BYTE, string[i], ERIAR_ASF);
287
         }
288
 }
289
 
290
-void rtl8168_asf_community_string_len(void __iomem *ioaddr, int arg, unsigned int *data)
291
+void rtl8168_asf_community_string_len(struct rtl8168_private *tp, int arg, unsigned int *data)
292
 {
293
         if (arg == ASF_GET)
294
-                data[ASFCOMMULEN] = rtl8168_eri_read(ioaddr, StringLength, RW_ONE_BYTE, ERIAR_ASF);
295
+                data[ASFCOMMULEN] = rtl8168_eri_read(tp, StringLength, RW_ONE_BYTE, ERIAR_ASF);
296
         else /* arg == ASF_SET */
297
-                rtl8168_eri_write(ioaddr, StringLength, RW_ONE_BYTE, data[ASFCOMMULEN], ERIAR_ASF);
298
+                rtl8168_eri_write(tp, StringLength, RW_ONE_BYTE, data[ASFCOMMULEN], ERIAR_ASF);
299
 }
300
 
301
-void rtl8168_asf_time_period(void __iomem *ioaddr, int arg, int offset, unsigned int *data)
302
+void rtl8168_asf_time_period(struct rtl8168_private *tp, int arg, int offset, unsigned int *data)
303
 {
304
         int pos = 0;
305
 
306
@@ -344,21 +342,20 @@
307
                 pos = ASFALERTRESND;
308
 
309
         if (arg == ASF_GET)
310
-                data[pos] = rtl8168_eri_read(ioaddr, offset, RW_ONE_BYTE, ERIAR_ASF);
311
+                data[pos] = rtl8168_eri_read(tp, offset, RW_ONE_BYTE, ERIAR_ASF);
312
         else /* arg == ASF_SET */
313
-                rtl8168_eri_write(ioaddr, offset, RW_ONE_BYTE, data[pos], ERIAR_ASF);
314
+                rtl8168_eri_write(tp, offset, RW_ONE_BYTE, data[pos], ERIAR_ASF);
315
 
316
 }
317
 
318
 void rtl8168_asf_key_access(struct rtl8168_private *tp, int arg, int offset, unsigned int *data)
319
 {
320
-        void __iomem *ioaddr=tp->mmio_addr;
321
         int i, j;
322
         int key_off = 0;
323
 
324
         if (arg == ASF_GET) {
325
                 for (i = 0; i < KEY_LEN; i++)
326
-                        data[i] = rtl8168_eri_read(ioaddr, offset + KEY_LEN - (i + 1), RW_ONE_BYTE, ERIAR_ASF);
327
+                        data[i] = rtl8168_eri_read(tp, offset + KEY_LEN - (i + 1), RW_ONE_BYTE, ERIAR_ASF);
328
         } else {
329
                 if (offset == KO)
330
                         key_off = 162;
331
@@ -371,7 +368,7 @@
332
 
333
                 /* arg == ASF_SET */
334
                 for (i = 0; i < KEY_LEN; i++)
335
-                        rtl8168_eri_write(ioaddr, offset + KEY_LEN - (i + 1), RW_ONE_BYTE, data[i], ERIAR_ASF);
336
+                        rtl8168_eri_write(tp, offset + KEY_LEN - (i + 1), RW_ONE_BYTE, data[i], ERIAR_ASF);
337
 
338
                 /* write the new key to EEPROM */
339
                 for (i = 0, j = 19; i < 10; i++, j = j - 2)
340
@@ -379,46 +376,46 @@
341
         }
342
 }
343
 
344
-void rtl8168_asf_rw_hexadecimal(void __iomem *ioaddr, int arg, int offset, int len, unsigned int *data)
345
+void rtl8168_asf_rw_hexadecimal(struct rtl8168_private *tp, int arg, int offset, int len, unsigned int *data)
346
 {
347
         if (arg == ASF_GET)
348
-                data[ASFRWHEXNUM] = rtl8168_eri_read(ioaddr, offset, len, ERIAR_ASF);
349
+                data[ASFRWHEXNUM] = rtl8168_eri_read(tp, offset, len, ERIAR_ASF);
350
         else /* arg == ASF_SET */
351
-                rtl8168_eri_write(ioaddr, offset, len, data[ASFRWHEXNUM], ERIAR_ASF);
352
+                rtl8168_eri_write(tp, offset, len, data[ASFRWHEXNUM], ERIAR_ASF);
353
 }
354
 
355
-void rtl8168_asf_rw_systemid(void __iomem *ioaddr, int arg, unsigned int *data)
356
+void rtl8168_asf_rw_systemid(struct rtl8168_private *tp, int arg, unsigned int *data)
357
 {
358
         int i;
359
 
360
         if (arg == ASF_GET)
361
                 for (i = 0; i < SYSID_LEN ; i++)
362
-                        data[i] = rtl8168_eri_read(ioaddr, SysID + i, RW_ONE_BYTE, ERIAR_ASF);
363
+                        data[i] = rtl8168_eri_read(tp, SysID + i, RW_ONE_BYTE, ERIAR_ASF);
364
         else /* arg == ASF_SET */
365
                 for (i = 0; i < SYSID_LEN ; i++)
366
-                        rtl8168_eri_write(ioaddr, SysID + i, RW_ONE_BYTE, data[i], ERIAR_ASF);
367
+                        rtl8168_eri_write(tp, SysID + i, RW_ONE_BYTE, data[i], ERIAR_ASF);
368
 }
369
 
370
-void rtl8168_asf_rw_iana(void __iomem *ioaddr, int arg, unsigned int *data)
371
+void rtl8168_asf_rw_iana(struct rtl8168_private *tp, int arg, unsigned int *data)
372
 {
373
         int i;
374
 
375
         if (arg == ASF_GET)
376
                 for (i = 0; i < RW_FOUR_BYTES; i++)
377
-                        data[i] = rtl8168_eri_read(ioaddr, IANA + i, RW_ONE_BYTE, ERIAR_ASF);
378
+                        data[i] = rtl8168_eri_read(tp, IANA + i, RW_ONE_BYTE, ERIAR_ASF);
379
         else /* arg == ASF_SET */
380
                 for (i = 0; i < RW_FOUR_BYTES; i++)
381
-                        rtl8168_eri_write(ioaddr, IANA + i, RW_ONE_BYTE, data[i], ERIAR_ASF);
382
+                        rtl8168_eri_write(tp, IANA + i, RW_ONE_BYTE, data[i], ERIAR_ASF);
383
 }
384
 
385
-void rtl8168_asf_rw_uuid(void __iomem *ioaddr, int arg, unsigned int *data)
386
+void rtl8168_asf_rw_uuid(struct rtl8168_private *tp, int arg, unsigned int *data)
387
 {
388
         int i, j;
389
 
390
         if (arg == ASF_GET)
391
                 for (i = UUID_LEN - 1, j = 0; i >= 0 ; i--, j++)
392
-                        data[j] = rtl8168_eri_read(ioaddr, UUID + i, RW_ONE_BYTE, ERIAR_ASF);
393
+                        data[j] = rtl8168_eri_read(tp, UUID + i, RW_ONE_BYTE, ERIAR_ASF);
394
         else /* arg == ASF_SET */
395
                 for (i = UUID_LEN - 1, j = 0; i >= 0 ; i--, j++)
396
-                        rtl8168_eri_write(ioaddr, UUID + i, RW_ONE_BYTE, data[j], ERIAR_ASF);
397
+                        rtl8168_eri_write(tp, UUID + i, RW_ONE_BYTE, data[j], ERIAR_ASF);
398
 }
399
r8168-8.047.05.tar.bz2/src/r8168_asf.h -> r8168-8.048.00.tar.bz2/src/r8168_asf.h Changed
32
 
1
@@ -277,18 +277,18 @@
2
 };
3
 
4
 int rtl8168_asf_ioctl(struct net_device *dev, struct ifreq *ifr);
5
-void rtl8168_asf_hbperiod(void __iomem *ioaddr, int arg, unsigned int *data);
6
-void rtl8168_asf_wd16rst(void __iomem *ioaddr, int arg, unsigned int *data);
7
+void rtl8168_asf_hbperiod(struct rtl8168_private *tp, int arg, unsigned int *data);
8
+void rtl8168_asf_wd16rst(struct rtl8168_private *tp, int arg, unsigned int *data);
9
 void rtl8168_asf_console_mac(struct rtl8168_private *, int arg, unsigned int *data);
10
 void rtl8168_asf_ip_address(struct rtl8168_private *, int arg, int offset, unsigned int *data);
11
-void rtl8168_asf_config_regs(void __iomem *ioaddr, int arg, int offset, unsigned int *data);
12
-void rtl8168_asf_capability_masks(void __iomem *ioaddr, int arg, int offset, unsigned int *data);
13
-void rtl8168_asf_community_string(void __iomem *ioaddr, int arg, char *string);
14
-void rtl8168_asf_community_string_len(void __iomem *ioaddr, int arg, unsigned int *data);
15
-void rtl8168_asf_alert_resend_interval(void __iomem *ioaddr, int arg, unsigned int *data);
16
-void rtl8168_asf_time_period(void __iomem *ioaddr, int arg, int offset, unsigned int *data);
17
+void rtl8168_asf_config_regs(struct rtl8168_private *tp, int arg, int offset, unsigned int *data);
18
+void rtl8168_asf_capability_masks(struct rtl8168_private *tp, int arg, int offset, unsigned int *data);
19
+void rtl8168_asf_community_string(struct rtl8168_private *tp, int arg, char *string);
20
+void rtl8168_asf_community_string_len(struct rtl8168_private *tp, int arg, unsigned int *data);
21
+void rtl8168_asf_alert_resend_interval(struct rtl8168_private *tp, int arg, unsigned int *data);
22
+void rtl8168_asf_time_period(struct rtl8168_private *tp, int arg, int offset, unsigned int *data);
23
 void rtl8168_asf_key_access(struct rtl8168_private *, int arg, int offset, unsigned int *data);
24
-void rtl8168_asf_rw_hexadecimal(void __iomem *ioaddr, int arg, int offset, int len, unsigned int *data);
25
-void rtl8168_asf_rw_iana(void __iomem *ioaddr, int arg, unsigned int *data);
26
-void rtl8168_asf_rw_uuid(void __iomem *ioaddr, int arg, unsigned int *data);
27
-void rtl8168_asf_rw_systemid(void __iomem *ioaddr, int arg, unsigned int *data);
28
+void rtl8168_asf_rw_hexadecimal(struct rtl8168_private *tp, int arg, int offset, int len, unsigned int *data);
29
+void rtl8168_asf_rw_iana(struct rtl8168_private *tp, int arg, unsigned int *data);
30
+void rtl8168_asf_rw_uuid(struct rtl8168_private *tp, int arg, unsigned int *data);
31
+void rtl8168_asf_rw_systemid(struct rtl8168_private *tp, int arg, unsigned int *data);
32
r8168-8.047.05.tar.bz2/src/r8168_dash.h -> r8168-8.048.00.tar.bz2/src/r8168_dash.h Changed
35
 
1
@@ -172,10 +172,10 @@
2
 #define OCP_REG_CONFIG0_DRV_WAIT_OOB     BIT_8
3
 #define OCP_REG_CONFIG0_TLSEN            BIT_7
4
 
5
-#define HW_DASH_SUPPORT_DASH(_M)        ((_M)->HwSuppDashVer > 0 )
6
-#define HW_DASH_SUPPORT_TYPE_1(_M)        ((_M)->HwSuppDashVer == 1 )
7
-#define HW_DASH_SUPPORT_TYPE_2(_M)        ((_M)->HwSuppDashVer == 2 )
8
-#define HW_DASH_SUPPORT_TYPE_3(_M)        ((_M)->HwSuppDashVer == 3 )
9
+#define HW_DASH_SUPPORT_DASH(_M)        ((_M)->HwSuppDashVer > 0)
10
+#define HW_DASH_SUPPORT_TYPE_1(_M)        ((_M)->HwSuppDashVer == 1)
11
+#define HW_DASH_SUPPORT_TYPE_2(_M)        ((_M)->HwSuppDashVer == 2)
12
+#define HW_DASH_SUPPORT_TYPE_3(_M)        ((_M)->HwSuppDashVer == 3)
13
 
14
 #define RECV_FROM_FW_BUF_SIZE (1520)
15
 #define SEND_TO_FW_BUF_SIZE (1520)
16
@@ -241,12 +241,12 @@
17
 #define CMAC_TXDESC_OFFSET 0x98    //TX: 0x98 - 0x9F
18
 
19
 /* cmac write/read MMIO register */
20
-#define RTL_CMAC_W8(reg, val8)   writeb ((val8), tp->cmac_ioaddr + (reg))
21
-#define RTL_CMAC_W16(reg, val16) writew ((val16), tp->cmac_ioaddr + (reg))
22
-#define RTL_CMAC_W32(reg, val32) writel ((val32), tp->cmac_ioaddr + (reg))
23
-#define RTL_CMAC_R8(reg)     readb (tp->cmac_ioaddr + (reg))
24
-#define RTL_CMAC_R16(reg)        readw (tp->cmac_ioaddr + (reg))
25
-#define RTL_CMAC_R32(reg)        ((unsigned long) readl (tp->cmac_ioaddr + (reg)))
26
+#define RTL_CMAC_W8(tp, reg, val8)   writeb ((val8), tp->cmac_ioaddr + (reg))
27
+#define RTL_CMAC_W16(tp, reg, val16) writew ((val16), tp->cmac_ioaddr + (reg))
28
+#define RTL_CMAC_W32(tp, reg, val32) writel ((val32), tp->cmac_ioaddr + (reg))
29
+#define RTL_CMAC_R8(tp, reg)     readb (tp->cmac_ioaddr + (reg))
30
+#define RTL_CMAC_R16(tp, reg)        readw (tp->cmac_ioaddr + (reg))
31
+#define RTL_CMAC_R32(tp, reg)        ((unsigned long) readl (tp->cmac_ioaddr + (reg)))
32
 
33
 int rtl8168_dash_ioctl(struct net_device *dev, struct ifreq *ifr);
34
 void HandleDashInterrupt(struct net_device *dev);
35
r8168-8.047.05.tar.bz2/src/r8168_n.c -> r8168-8.048.00.tar.bz2/src/r8168_n.c Changed
5813
 
1
@@ -35,6 +35,10 @@
2
  * This driver is modified from r8169.c in Linux kernel 2.6.18
3
  */
4
 
5
+/* In Linux 5.4 asm_inline was introduced, but it's not supported by clang.
6
+ * Redefine it to just asm to enable successful compilation.
7
+ */
8
+
9
 #include <linux/module.h>
10
 #include <linux/version.h>
11
 #include <linux/pci.h>
12
@@ -57,8 +61,10 @@
13
 #include <linux/completion.h>
14
 
15
 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26)
16
+#if LINUX_VERSION_CODE < KERNEL_VERSION(5,4,0)
17
 #include <linux/pci-aspm.h>
18
 #endif
19
+#endif
20
 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,37)
21
 #include <linux/prefetch.h>
22
 #endif
23
@@ -293,6 +299,12 @@
24
         0xff7e5880,
25
         Jumbo_Frame_9k),
26
 
27
+        _R("RTL8168FP/8111FP",
28
+        CFG_METHOD_33,
29
+        RxCfg_128_int_en | RxEarly_off_V2 | Rx_Single_fetch_V2 | (RX_DMA_BURST << RxCfgDMAShift),
30
+        0xff7e5880,
31
+        Jumbo_Frame_9k),
32
+
33
         _R("Unknown",
34
         CFG_METHOD_DEFAULT,
35
         (RX_DMA_BURST << RxCfgDMAShift),
36
@@ -446,7 +458,7 @@
37
 static void rtl8168_set_rx_mode(struct net_device *dev);
38
 static void rtl8168_tx_timeout(struct net_device *dev);
39
 static struct net_device_stats *rtl8168_get_stats(struct net_device *dev);
40
-static int rtl8168_rx_interrupt(struct net_device *, struct rtl8168_private *, void __iomem *, napi_budget);
41
+static int rtl8168_rx_interrupt(struct net_device *, struct rtl8168_private *, napi_budget);
42
 static int rtl8168_change_mtu(struct net_device *dev, int new_mtu);
43
 static void rtl8168_down(struct net_device *dev);
44
 
45
@@ -882,7 +894,7 @@
46
         seq_printf(m, "aspm\t0x%x\n", aspm);
47
         seq_printf(m, "s5wol\t0x%x\n", s5wol);
48
         seq_printf(m, "s5_keep_curr_mac\t0x%x\n", s5_keep_curr_mac);
49
-        seq_printf(m, "eee_enable\t0x%x\n", eee_enable);
50
+        seq_printf(m, "eee_enable\t0x%x\n", tp->eee_enabled);
51
         seq_printf(m, "hwoptimize\t0x%lx\n", hwoptimize);
52
         seq_printf(m, "proc_init_num\t0x%x\n", proc_init_num);
53
         seq_printf(m, "s0_magic_packet\t0x%x\n", s0_magic_packet);
54
@@ -906,7 +918,6 @@
55
 {
56
         struct net_device *dev = m->private;
57
         struct rtl8168_private *tp = netdev_priv(dev);
58
-        void __iomem *ioaddr = tp->mmio_addr;
59
         struct rtl8168_counters *counters;
60
         dma_addr_t paddr;
61
         u32 cmd;
62
@@ -925,13 +936,13 @@
63
         }
64
 
65
         spin_lock_irqsave(&tp->lock, flags);
66
-        RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
67
+        RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32);
68
         cmd = (u64)paddr & DMA_BIT_MASK(32);
69
-        RTL_W32(CounterAddrLow, cmd);
70
-        RTL_W32(CounterAddrLow, cmd | CounterDump);
71
+        RTL_W32(tp, CounterAddrLow, cmd);
72
+        RTL_W32(tp, CounterAddrLow, cmd | CounterDump);
73
 
74
         WaitCnt = 0;
75
-        while (RTL_R32(CounterAddrLow) & CounterDump) {
76
+        while (RTL_R32(tp, CounterAddrLow) & CounterDump) {
77
                 udelay(10);
78
 
79
                 WaitCnt++;
80
@@ -991,7 +1002,6 @@
81
         int i, n, max = R8168_EPHY_REGS_SIZE/2;
82
         u16 word_rd;
83
         struct rtl8168_private *tp = netdev_priv(dev);
84
-        void __iomem *ioaddr = tp->mmio_addr;
85
         unsigned long flags;
86
 
87
         seq_puts(m, "\nDump PCIE PHY\n");
88
@@ -1002,7 +1012,7 @@
89
                 seq_printf(m, "\n0x%02x:\t", n);
90
 
91
                 for (i = 0; i < 8 && n < max; i++, n++) {
92
-                        word_rd = rtl8168_ephy_read(ioaddr, n);
93
+                        word_rd = rtl8168_ephy_read(tp, n);
94
                         seq_printf(m, "%04x ", word_rd);
95
                 }
96
         }
97
@@ -1046,7 +1056,6 @@
98
         int i, n, max = R8168_ERI_REGS_SIZE;
99
         u32 dword_rd;
100
         struct rtl8168_private *tp = netdev_priv(dev);
101
-        void __iomem *ioaddr = tp->mmio_addr;
102
         unsigned long flags;
103
 
104
         switch (tp->mcfg) {
105
@@ -1066,7 +1075,7 @@
106
                 seq_printf(m, "\n0x%02x:\t", n);
107
 
108
                 for (i = 0; i < 4 && n < max; i++, n+=4) {
109
-                        dword_rd = rtl8168_eri_read(ioaddr, n, 4, ERIAR_ExGMAC);
110
+                        dword_rd = rtl8168_eri_read(tp, n, 4, ERIAR_ExGMAC);
111
                         seq_printf(m, "%08x ", dword_rd);
112
                 }
113
         }
114
@@ -1274,7 +1283,7 @@
115
                         aspm,
116
                         s5wol,
117
                         s5_keep_curr_mac,
118
-                        eee_enable,
119
+                        tp->eee_enabled,
120
                         hwoptimize,
121
                         proc_init_num,
122
                         s0_magic_packet,
123
@@ -1303,7 +1312,6 @@
124
 {
125
         struct net_device *dev = data;
126
         struct rtl8168_private *tp = netdev_priv(dev);
127
-        void __iomem *ioaddr = tp->mmio_addr;
128
         struct rtl8168_counters *counters;
129
         dma_addr_t paddr;
130
         u32 cmd;
131
@@ -1325,13 +1333,13 @@
132
         }
133
 
134
         spin_lock_irqsave(&tp->lock, flags);
135
-        RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
136
+        RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32);
137
         cmd = (u64)paddr & DMA_BIT_MASK(32);
138
-        RTL_W32(CounterAddrLow, cmd);
139
-        RTL_W32(CounterAddrLow, cmd | CounterDump);
140
+        RTL_W32(tp, CounterAddrLow, cmd);
141
+        RTL_W32(tp, CounterAddrLow, cmd | CounterDump);
142
 
143
         WaitCnt = 0;
144
-        while (RTL_R32(CounterAddrLow) & CounterDump) {
145
+        while (RTL_R32(tp, CounterAddrLow) & CounterDump) {
146
                 udelay(10);
147
 
148
                 WaitCnt++;
149
@@ -1421,7 +1429,6 @@
150
         int i, n, max = R8168_EPHY_REGS_SIZE/2;
151
         u16 word_rd;
152
         struct rtl8168_private *tp = netdev_priv(dev);
153
-        void __iomem *ioaddr = tp->mmio_addr;
154
         unsigned long flags;
155
         int len = 0;
156
 
157
@@ -1436,7 +1443,7 @@
158
                                 n);
159
 
160
                 for (i = 0; i < 8 && n < max; i++, n++) {
161
-                        word_rd = rtl8168_ephy_read(ioaddr, n);
162
+                        word_rd = rtl8168_ephy_read(tp, n);
163
                         len += snprintf(page + len, count - len,
164
                                         "%04x ",
165
                                         word_rd);
166
@@ -1497,7 +1504,6 @@
167
         int i, n, max = R8168_ERI_REGS_SIZE;
168
         u32 dword_rd;
169
         struct rtl8168_private *tp = netdev_priv(dev);
170
-        void __iomem *ioaddr = tp->mmio_addr;
171
         unsigned long flags;
172
         int len = 0;
173
 
174
@@ -1523,7 +1529,7 @@
175
                                 n);
176
 
177
                 for (i = 0; i < 4 && n < max; i++, n+=4) {
178
-                        dword_rd = rtl8168_eri_read(ioaddr, n, 4, ERIAR_ExGMAC);
179
+                        dword_rd = rtl8168_eri_read(tp, n, 4, ERIAR_ExGMAC);
180
                         len += snprintf(page + len, count - len,
181
                                         "%08x ",
182
                                         dword_rd);
183
@@ -1750,10 +1756,11 @@
184
                 u32 RegAddr,
185
                 u32 value)
186
 {
187
-        void __iomem *ioaddr = tp->mmio_addr;
188
         u32 data32;
189
         int i;
190
 
191
+        if (tp->HwSuppPhyOcpVer == 0) goto out;
192
+
193
 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,18)
194
         WARN_ON_ONCE(RegAddr % 2);
195
 #endif
196
@@ -1761,13 +1768,15 @@
197
         data32 <<= OCPR_Addr_Reg_shift;
198
         data32 |= OCPR_Write | value;
199
 
200
-        RTL_W32(PHYOCP, data32);
201
+        RTL_W32(tp, PHYOCP, data32);
202
         for (i = 0; i < 100; i++) {
203
                 udelay(1);
204
 
205
-                if (!(RTL_R32(PHYOCP) & OCPR_Flag))
206
+                if (!(RTL_R32(tp, PHYOCP) & OCPR_Flag))
207
                         break;
208
         }
209
+out:
210
+        return;
211
 }
212
 
213
 static void mdio_direct_write_phy_ocp(struct rtl8168_private *tp,
214
@@ -1809,7 +1818,6 @@
215
                             u32 RegAddr,
216
                             u32 value)
217
 {
218
-        void __iomem *ioaddr = tp->mmio_addr;
219
         int i;
220
 
221
         if (RegAddr == 0x1F) {
222
@@ -1817,47 +1825,44 @@
223
         }
224
 
225
         if (tp->mcfg == CFG_METHOD_11) {
226
-                RTL_W32(OCPDR, OCPDR_Write |
227
+                RTL_W32(tp, OCPDR, OCPDR_Write |
228
                         (RegAddr & OCPDR_Reg_Mask) << OCPDR_GPHY_Reg_shift |
229
                         (value & OCPDR_Data_Mask));
230
-                RTL_W32(OCPAR, OCPAR_GPHY_Write);
231
-                RTL_W32(EPHY_RXER_NUM, 0);
232
+                RTL_W32(tp, OCPAR, OCPAR_GPHY_Write);
233
+                RTL_W32(tp, EPHY_RXER_NUM, 0);
234
 
235
                 for (i = 0; i < 100; i++) {
236
                         mdelay(1);
237
-                        if (!(RTL_R32(OCPAR) & OCPAR_Flag))
238
+                        if (!(RTL_R32(tp, OCPAR) & OCPAR_Flag))
239
                                 break;
240
                 }
241
-        } else if (tp->mcfg == CFG_METHOD_21 || tp->mcfg == CFG_METHOD_22 ||
242
-                   tp->mcfg == CFG_METHOD_23 || tp->mcfg == CFG_METHOD_24 ||
243
-                   tp->mcfg == CFG_METHOD_25 || tp->mcfg == CFG_METHOD_26 ||
244
-                   tp->mcfg == CFG_METHOD_27 || tp->mcfg == CFG_METHOD_28 ||
245
-                   tp->mcfg == CFG_METHOD_29 || tp->mcfg == CFG_METHOD_30 ||
246
-                   tp->mcfg == CFG_METHOD_31 || tp->mcfg == CFG_METHOD_32) {
247
-                if (RegAddr == 0x1F) {
248
-                        return;
249
-                }
250
-                rtl8168_mdio_real_write_phy_ocp(tp, tp->cur_page, RegAddr, value);
251
         } else {
252
-                if (tp->mcfg == CFG_METHOD_12 || tp->mcfg == CFG_METHOD_13)
253
-                        RTL_W32(0xD0, RTL_R32(0xD0) & ~0x00020000);
254
-
255
-                RTL_W32(PHYAR, PHYAR_Write |
256
-                        (RegAddr & PHYAR_Reg_Mask) << PHYAR_Reg_shift |
257
-                        (value & PHYAR_Data_Mask));
258
-
259
-                for (i = 0; i < 10; i++) {
260
-                        udelay(100);
261
+                if (tp->HwSuppPhyOcpVer > 0) {
262
+                        if (RegAddr == 0x1F) {
263
+                                return;
264
+                        }
265
+                        rtl8168_mdio_real_write_phy_ocp(tp, tp->cur_page, RegAddr, value);
266
+                } else {
267
+                        if (tp->mcfg == CFG_METHOD_12 || tp->mcfg == CFG_METHOD_13)
268
+                                RTL_W32(tp, 0xD0, RTL_R32(tp, 0xD0) & ~0x00020000);
269
 
270
-                        /* Check if the RTL8168 has completed writing to the specified MII register */
271
-                        if (!(RTL_R32(PHYAR) & PHYAR_Flag)) {
272
-                                udelay(20);
273
-                                break;
274
+                        RTL_W32(tp, PHYAR, PHYAR_Write |
275
+                                (RegAddr & PHYAR_Reg_Mask) << PHYAR_Reg_shift |
276
+                                (value & PHYAR_Data_Mask));
277
+
278
+                        for (i = 0; i < 10; i++) {
279
+                                udelay(100);
280
+
281
+                                /* Check if the RTL8168 has completed writing to the specified MII register */
282
+                                if (!(RTL_R32(tp, PHYAR) & PHYAR_Flag)) {
283
+                                        udelay(20);
284
+                                        break;
285
+                                }
286
                         }
287
-                }
288
 
289
-                if (tp->mcfg == CFG_METHOD_12 || tp->mcfg == CFG_METHOD_13)
290
-                        RTL_W32(0xD0, RTL_R32(0xD0) | 0x00020000);
291
+                        if (tp->mcfg == CFG_METHOD_12 || tp->mcfg == CFG_METHOD_13)
292
+                                RTL_W32(tp, 0xD0, RTL_R32(tp, 0xD0) | 0x00020000);
293
+                }
294
         }
295
 }
296
 
297
@@ -1887,25 +1892,27 @@
298
 static u32 mdio_real_direct_read_phy_ocp(struct rtl8168_private *tp,
299
                 u32 RegAddr)
300
 {
301
-        void __iomem *ioaddr = tp->mmio_addr;
302
         u32 data32;
303
         int i, value = 0;
304
 
305
+        if (tp->HwSuppPhyOcpVer == 0) goto out;
306
+
307
 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,18)
308
         WARN_ON_ONCE(RegAddr % 2);
309
 #endif
310
         data32 = RegAddr/2;
311
         data32 <<= OCPR_Addr_Reg_shift;
312
 
313
-        RTL_W32(PHYOCP, data32);
314
+        RTL_W32(tp, PHYOCP, data32);
315
         for (i = 0; i < 100; i++) {
316
                 udelay(1);
317
 
318
-                if (RTL_R32(PHYOCP) & OCPR_Flag)
319
+                if (RTL_R32(tp, PHYOCP) & OCPR_Flag)
320
                         break;
321
         }
322
-        value = RTL_R32(PHYOCP) & OCPDR_Data_Mask;
323
+        value = RTL_R32(tp, PHYOCP) & OCPDR_Data_Mask;
324
 
325
+out:
326
         return value;
327
 }
328
 
329
@@ -1944,59 +1951,55 @@
330
 u32 mdio_real_read(struct rtl8168_private *tp,
331
                    u32 RegAddr)
332
 {
333
-        void __iomem *ioaddr = tp->mmio_addr;
334
         int i, value = 0;
335
 
336
         if (tp->mcfg==CFG_METHOD_11) {
337
-                RTL_W32(OCPDR, OCPDR_Read |
338
+                RTL_W32(tp, OCPDR, OCPDR_Read |
339
                         (RegAddr & OCPDR_Reg_Mask) << OCPDR_GPHY_Reg_shift);
340
-                RTL_W32(OCPAR, OCPAR_GPHY_Write);
341
-                RTL_W32(EPHY_RXER_NUM, 0);
342
+                RTL_W32(tp, OCPAR, OCPAR_GPHY_Write);
343
+                RTL_W32(tp, EPHY_RXER_NUM, 0);
344
 
345
                 for (i = 0; i < 100; i++) {
346
                         mdelay(1);
347
-                        if (!(RTL_R32(OCPAR) & OCPAR_Flag))
348
+                        if (!(RTL_R32(tp, OCPAR) & OCPAR_Flag))
349
                                 break;
350
                 }
351
 
352
                 mdelay(1);
353
-                RTL_W32(OCPAR, OCPAR_GPHY_Read);
354
-                RTL_W32(EPHY_RXER_NUM, 0);
355
+                RTL_W32(tp, OCPAR, OCPAR_GPHY_Read);
356
+                RTL_W32(tp, EPHY_RXER_NUM, 0);
357
 
358
                 for (i = 0; i < 100; i++) {
359
                         mdelay(1);
360
-                        if (RTL_R32(OCPAR) & OCPAR_Flag)
361
+                        if (RTL_R32(tp, OCPAR) & OCPAR_Flag)
362
                                 break;
363
                 }
364
 
365
-                value = RTL_R32(OCPDR) & OCPDR_Data_Mask;
366
-        } else if (tp->mcfg == CFG_METHOD_21 || tp->mcfg == CFG_METHOD_22 ||
367
-                   tp->mcfg == CFG_METHOD_23 || tp->mcfg == CFG_METHOD_24 ||
368
-                   tp->mcfg == CFG_METHOD_25 || tp->mcfg == CFG_METHOD_26 ||
369
-                   tp->mcfg == CFG_METHOD_27 || tp->mcfg == CFG_METHOD_28 ||
370
-                   tp->mcfg == CFG_METHOD_29 || tp->mcfg == CFG_METHOD_30 ||
371
-                   tp->mcfg == CFG_METHOD_31 || tp->mcfg == CFG_METHOD_32) {
372
-                value = rtl8168_mdio_real_read_phy_ocp(tp, tp->cur_page, RegAddr);
373
+                value = RTL_R32(tp, OCPDR) & OCPDR_Data_Mask;
374
         } else {
375
-                if (tp->mcfg == CFG_METHOD_12 || tp->mcfg == CFG_METHOD_13)
376
-                        RTL_W32(0xD0, RTL_R32(0xD0) & ~0x00020000);
377
+                if (tp->HwSuppPhyOcpVer > 0) {
378
+                        value = rtl8168_mdio_real_read_phy_ocp(tp, tp->cur_page, RegAddr);
379
+                } else {
380
+                        if (tp->mcfg == CFG_METHOD_12 || tp->mcfg == CFG_METHOD_13)
381
+                                RTL_W32(tp, 0xD0, RTL_R32(tp, 0xD0) & ~0x00020000);
382
 
383
-                RTL_W32(PHYAR,
384
-                        PHYAR_Read | (RegAddr & PHYAR_Reg_Mask) << PHYAR_Reg_shift);
385
+                        RTL_W32(tp, PHYAR,
386
+                                PHYAR_Read | (RegAddr & PHYAR_Reg_Mask) << PHYAR_Reg_shift);
387
 
388
-                for (i = 0; i < 10; i++) {
389
-                        udelay(100);
390
+                        for (i = 0; i < 10; i++) {
391
+                                udelay(100);
392
 
393
-                        /* Check if the RTL8168 has completed retrieving data from the specified MII register */
394
-                        if (RTL_R32(PHYAR) & PHYAR_Flag) {
395
-                                value = RTL_R32(PHYAR) & PHYAR_Data_Mask;
396
-                                udelay(20);
397
-                                break;
398
+                                /* Check if the RTL8168 has completed retrieving data from the specified MII register */
399
+                                if (RTL_R32(tp, PHYAR) & PHYAR_Flag) {
400
+                                        value = RTL_R32(tp, PHYAR) & PHYAR_Data_Mask;
401
+                                        udelay(20);
402
+                                        break;
403
+                                }
404
                         }
405
-                }
406
 
407
-                if (tp->mcfg == CFG_METHOD_12 || tp->mcfg == CFG_METHOD_13)
408
-                        RTL_W32(0xD0, RTL_R32(0xD0) | 0x00020000);
409
+                        if (tp->mcfg == CFG_METHOD_12 || tp->mcfg == CFG_METHOD_13)
410
+                                RTL_W32(tp, 0xD0, RTL_R32(tp, 0xD0) | 0x00020000);
411
+                }
412
         }
413
 
414
         return value;
415
@@ -2053,7 +2056,6 @@
416
 
417
 void rtl8168_mac_ocp_write(struct rtl8168_private *tp, u16 reg_addr, u16 value)
418
 {
419
-        void __iomem *ioaddr = tp->mmio_addr;
420
         u32 data32;
421
 
422
 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,18)
423
@@ -2065,12 +2067,11 @@
424
         data32 += value;
425
         data32 |= OCPR_Write;
426
 
427
-        RTL_W32(MACOCP, data32);
428
+        RTL_W32(tp, MACOCP, data32);
429
 }
430
 
431
 u16 rtl8168_mac_ocp_read(struct rtl8168_private *tp, u16 reg_addr)
432
 {
433
-        void __iomem *ioaddr = tp->mmio_addr;
434
         u32 data32;
435
         u16 data16 = 0;
436
 
437
@@ -2081,15 +2082,14 @@
438
         data32 = reg_addr/2;
439
         data32 <<= OCPR_Addr_Reg_shift;
440
 
441
-        RTL_W32(MACOCP, data32);
442
-        data16 = (u16)RTL_R32(MACOCP);
443
+        RTL_W32(tp, MACOCP, data32);
444
+        data16 = (u16)RTL_R32(tp, MACOCP);
445
 
446
         return data16;
447
 }
448
 
449
 static u32 real_ocp_read(struct rtl8168_private *tp, u16 addr, u8 len)
450
 {
451
-        void __iomem *ioaddr = tp->mmio_addr;
452
         int i, val_shift, shift = 0;
453
         u32 value1 = 0, value2 = 0, mask;
454
 
455
@@ -2100,11 +2100,11 @@
456
                 val_shift = addr % 4;
457
                 addr = addr & ~0x3;
458
 
459
-                RTL_W32(OCPAR, (0x0F<<12) | (addr&0xFFF));
460
+                RTL_W32(tp, OCPAR, (0x0F<<12) | (addr&0xFFF));
461
 
462
                 for (i = 0; i < 20; i++) {
463
                         udelay(100);
464
-                        if (RTL_R32(OCPAR) & OCPAR_Flag)
465
+                        if (RTL_R32(tp, OCPAR) & OCPAR_Flag)
466
                                 break;
467
                 }
468
 
469
@@ -2113,7 +2113,7 @@
470
                 else if (len == 3)  mask = (0xFFFFFF << (val_shift * 8)) & 0xFFFFFFFF;
471
                 else            mask = (0xFFFFFFFF << (val_shift * 8)) & 0xFFFFFFFF;
472
 
473
-                value1 = RTL_R32(OCPDR) & mask;
474
+                value1 = RTL_R32(tp, OCPDR) & mask;
475
                 value2 |= (value1 >> val_shift * 8) << shift * 8;
476
 
477
                 if (len <= 4 - val_shift) {
478
@@ -2132,9 +2132,7 @@
479
 
480
 u32 rtl8168_ocp_read_with_oob_base_address(struct rtl8168_private *tp, u16 addr, u8 len, const u32 base_address)
481
 {
482
-        void __iomem *ioaddr = tp->mmio_addr;
483
-
484
-        return rtl8168_eri_read_with_oob_base_address(ioaddr, addr, len, ERIAR_OOB, base_address);
485
+        return rtl8168_eri_read_with_oob_base_address(tp, addr, len, ERIAR_OOB, base_address);
486
 }
487
 
488
 u32 rtl8168_ocp_read(struct rtl8168_private *tp, u16 addr, u8 len)
489
@@ -2153,7 +2151,6 @@
490
 
491
 static int real_ocp_write(struct rtl8168_private *tp, u16 addr, u8 len, u32 value)
492
 {
493
-        void __iomem *ioaddr = tp->mmio_addr;
494
         int i, val_shift, shift = 0;
495
         u32 value1 = 0, mask;
496
 
497
@@ -2172,14 +2169,14 @@
498
                 value1 = rtl8168_ocp_read(tp, addr, 4) & ~mask;
499
                 value1 |= ((value << val_shift * 8) >> shift * 8);
500
 
501
-                RTL_W32(OCPDR, value1);
502
-                RTL_W32(OCPAR, OCPAR_Flag | (0x0F<<12) | (addr&0xFFF));
503
+                RTL_W32(tp, OCPDR, value1);
504
+                RTL_W32(tp, OCPAR, OCPAR_Flag | (0x0F<<12) | (addr&0xFFF));
505
 
506
                 for (i = 0; i < 10; i++) {
507
                         udelay(100);
508
 
509
                         /* Check if the RTL8168 has completed ERI write */
510
-                        if (!(RTL_R32(OCPAR) & OCPAR_Flag))
511
+                        if (!(RTL_R32(tp, OCPAR) & OCPAR_Flag))
512
                                 break;
513
                 }
514
 
515
@@ -2199,9 +2196,7 @@
516
 
517
 u32 rtl8168_ocp_write_with_oob_base_address(struct rtl8168_private *tp, u16 addr, u8 len, u32 value, const u32 base_address)
518
 {
519
-        void __iomem *ioaddr = tp->mmio_addr;
520
-
521
-        return rtl8168_eri_write_with_oob_base_address(ioaddr, addr, len, value, ERIAR_OOB, base_address);
522
+        return rtl8168_eri_write_with_oob_base_address(tp, addr, len, value, ERIAR_OOB, base_address);
523
 }
524
 
525
 void rtl8168_ocp_write(struct rtl8168_private *tp, u16 addr, u8 len, u32 value)
526
@@ -2241,6 +2236,7 @@
527
         case CFG_METHOD_28:
528
         case CFG_METHOD_31:
529
         case CFG_METHOD_32:
530
+        case CFG_METHOD_33:
531
         default:
532
                 ocp_reg_mutex_oob = 0x110;
533
                 ocp_reg_mutex_ib = 0x114;
534
@@ -2302,6 +2298,7 @@
535
         case CFG_METHOD_28:
536
         case CFG_METHOD_31:
537
         case CFG_METHOD_32:
538
+        case CFG_METHOD_33:
539
         default:
540
                 ocp_reg_mutex_oob = 0x110;
541
                 ocp_reg_mutex_ib = 0x114;
542
@@ -2315,9 +2312,7 @@
543
 
544
 void rtl8168_oob_notify(struct rtl8168_private *tp, u8 cmd)
545
 {
546
-        void __iomem *ioaddr = tp->mmio_addr;
547
-
548
-        rtl8168_eri_write(ioaddr, 0xE8, 1, cmd, ERIAR_ExGMAC);
549
+        rtl8168_eri_write(tp, 0xE8, 1, cmd, ERIAR_ExGMAC);
550
 
551
         rtl8168_ocp_write(tp, 0x30, 1, 0x01);
552
 }
553
@@ -2353,12 +2348,12 @@
554
                 u8 TmpUchar;
555
 
556
                 //Disable oob Tx
557
-                RTL_CMAC_W8(CMAC_IBCR2, RTL_CMAC_R8(CMAC_IBCR2) & ~( BIT_0 ));
558
+                RTL_CMAC_W8(tp, CMAC_IBCR2, RTL_CMAC_R8(tp, CMAC_IBCR2) & ~( BIT_0 ));
559
                 WaitCnt = 0;
560
 
561
                 //wait oob tx disable
562
                 do {
563
-                        TmpUchar = RTL_CMAC_R8(CMAC_IBISR0);
564
+                        TmpUchar = RTL_CMAC_R8(tp, CMAC_IBISR0);
565
 
566
                         if ( TmpUchar & ISRIMR_DASH_TYPE2_TX_DISABLE_IDLE ) {
567
                                 break;
568
@@ -2369,7 +2364,7 @@
569
                 } while(WaitCnt < 2000);
570
 
571
                 //Clear ISRIMR_DASH_TYPE2_TX_DISABLE_IDLE
572
-                RTL_CMAC_W8(CMAC_IBISR0, RTL_CMAC_R8(CMAC_IBISR0) | ISRIMR_DASH_TYPE2_TX_DISABLE_IDLE);
573
+                RTL_CMAC_W8(tp, CMAC_IBISR0, RTL_CMAC_R8(tp, CMAC_IBISR0) | ISRIMR_DASH_TYPE2_TX_DISABLE_IDLE);
574
         }
575
 }
576
 
577
@@ -2378,7 +2373,7 @@
578
         if (!tp->DASH) return;
579
 
580
         if (HW_DASH_SUPPORT_TYPE_2(tp) || HW_DASH_SUPPORT_TYPE_3(tp)) {
581
-                RTL_CMAC_W8(CMAC_IBCR2, RTL_CMAC_R8(CMAC_IBCR2) | BIT_0);
582
+                RTL_CMAC_W8(tp, CMAC_IBCR2, RTL_CMAC_R8(tp, CMAC_IBCR2) | BIT_0);
583
         }
584
 }
585
 
586
@@ -2387,7 +2382,7 @@
587
         if (!tp->DASH) return;
588
 
589
         if (HW_DASH_SUPPORT_TYPE_2(tp) || HW_DASH_SUPPORT_TYPE_3(tp)) {
590
-                RTL_CMAC_W8(CMAC_IBCR0, RTL_CMAC_R8(CMAC_IBCR0) & ~( BIT_0 ));
591
+                RTL_CMAC_W8(tp, CMAC_IBCR0, RTL_CMAC_R8(tp, CMAC_IBCR0) & ~( BIT_0 ));
592
         }
593
 }
594
 
595
@@ -2396,7 +2391,7 @@
596
         if (!tp->DASH) return;
597
 
598
         if (HW_DASH_SUPPORT_TYPE_2(tp) || HW_DASH_SUPPORT_TYPE_3(tp)) {
599
-                RTL_CMAC_W8(CMAC_IBCR0, RTL_CMAC_R8(CMAC_IBCR0) | BIT_0);
600
+                RTL_CMAC_W8(tp, CMAC_IBCR0, RTL_CMAC_R8(tp, CMAC_IBCR0) | BIT_0);
601
         }
602
 }
603
 
604
@@ -2410,102 +2405,11 @@
605
         }
606
 }
607
 
608
-static void rtl8168_driver_start(struct rtl8168_private *tp)
609
-{
610
-        void __iomem *ioaddr = tp->mmio_addr;
611
-
612
-        if (!tp->DASH)
613
-                return;
614
-
615
-        if (HW_DASH_SUPPORT_TYPE_2(tp) || HW_DASH_SUPPORT_TYPE_3(tp)) {
616
-                int timeout;
617
-                u32 tmp_value;
618
-
619
-                rtl8168_ocp_write(tp, 0x180, 1, OOB_CMD_DRIVER_START);
620
-                tmp_value = rtl8168_ocp_read(tp, 0x30, 1);
621
-                tmp_value |= BIT_0;
622
-                rtl8168_ocp_write(tp, 0x30, 1, tmp_value);
623
-
624
-                for (timeout = 0; timeout < 10; timeout++) {
625
-                        mdelay(10);
626
-                        if (rtl8168_ocp_read(tp, 0x124, 1) & BIT_0)
627
-                                break;
628
-                }
629
-        } else {
630
-                int timeout;
631
-                u32 reg;
632
-
633
-                if (tp->mcfg == CFG_METHOD_13) {
634
-                        RTL_W8(TwiCmdReg, RTL_R8(TwiCmdReg) | ( BIT_7 ));
635
-                }
636
-
637
-                rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
638
-
639
-                if (tp->mcfg == CFG_METHOD_13)
640
-                        reg = 0xB8;
641
-                else
642
-                        reg = 0x10;
643
-
644
-                for (timeout = 0; timeout < 10; timeout++) {
645
-                        mdelay(10);
646
-                        if (rtl8168_ocp_read(tp, reg, 2) & BIT_11)
647
-                                break;
648
-                }
649
-        }
650
-}
651
-
652
-static void rtl8168_driver_stop(struct rtl8168_private *tp)
653
-{
654
-        void __iomem *ioaddr = tp->mmio_addr;
655
-
656
-        if (!tp->DASH)
657
-                return;
658
-
659
-        if (HW_DASH_SUPPORT_TYPE_2(tp) || HW_DASH_SUPPORT_TYPE_3(tp)) {
660
-                struct net_device *dev = tp->dev;
661
-                int timeout;
662
-                u32 tmp_value;
663
-
664
-                rtl8168_dash2_disable_txrx(dev);
665
-
666
-                rtl8168_ocp_write(tp, 0x180, 1, OOB_CMD_DRIVER_STOP);
667
-                tmp_value = rtl8168_ocp_read(tp, 0x30, 1);
668
-                tmp_value |= BIT_0;
669
-                rtl8168_ocp_write(tp, 0x30, 1, tmp_value);
670
-
671
-                for (timeout = 0; timeout < 10; timeout++) {
672
-                        mdelay(10);
673
-                        if (!(rtl8168_ocp_read(tp, 0x124, 1) & BIT_0))
674
-                                break;
675
-                }
676
-        } else {
677
-                int timeout;
678
-                u32 reg;
679
-
680
-                rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
681
-
682
-                if (tp->mcfg == CFG_METHOD_13)
683
-                        reg = 0xB8;
684
-                else
685
-                        reg = 0x10;
686
-
687
-                for (timeout = 0; timeout < 10; timeout++) {
688
-                        mdelay(10);
689
-                        if ((rtl8168_ocp_read(tp, reg, 2) & BIT_11) == 0)
690
-                                break;
691
-                }
692
-
693
-                if (tp->mcfg == CFG_METHOD_13) {
694
-                        RTL_W8(TwiCmdReg, RTL_R8(TwiCmdReg) & ~( BIT_7 ));
695
-                }
696
-        }
697
-}
698
-
699
-void rtl8168_ephy_write(void __iomem *ioaddr, int RegAddr, int value)
700
+void rtl8168_ephy_write(struct rtl8168_private *tp, int RegAddr, int value)
701
 {
702
         int i;
703
 
704
-        RTL_W32(EPHYAR,
705
+        RTL_W32(tp, EPHYAR,
706
                 EPHYAR_Write |
707
                 (RegAddr & EPHYAR_Reg_Mask) << EPHYAR_Reg_shift |
708
                 (value & EPHYAR_Data_Mask));
709
@@ -2514,27 +2418,27 @@
710
                 udelay(100);
711
 
712
                 /* Check if the RTL8168 has completed EPHY write */
713
-                if (!(RTL_R32(EPHYAR) & EPHYAR_Flag))
714
+                if (!(RTL_R32(tp, EPHYAR) & EPHYAR_Flag))
715
                         break;
716
         }
717
 
718
         udelay(20);
719
 }
720
 
721
-u16 rtl8168_ephy_read(void __iomem *ioaddr, int RegAddr)
722
+u16 rtl8168_ephy_read(struct rtl8168_private *tp, int RegAddr)
723
 {
724
         int i;
725
         u16 value = 0xffff;
726
 
727
-        RTL_W32(EPHYAR,
728
+        RTL_W32(tp, EPHYAR,
729
                 EPHYAR_Read | (RegAddr & EPHYAR_Reg_Mask) << EPHYAR_Reg_shift);
730
 
731
         for (i = 0; i < 10; i++) {
732
                 udelay(100);
733
 
734
                 /* Check if the RTL8168 has completed EPHY read */
735
-                if (RTL_R32(EPHYAR) & EPHYAR_Flag) {
736
-                        value = (u16) (RTL_R32(EPHYAR) & EPHYAR_Data_Mask);
737
+                if (RTL_R32(tp, EPHYAR) & EPHYAR_Flag) {
738
+                        value = (u16) (RTL_R32(tp, EPHYAR) & EPHYAR_Data_Mask);
739
                         break;
740
                 }
741
         }
742
@@ -2546,13 +2450,12 @@
743
 
744
 static void ClearAndSetPCIePhyBit(struct rtl8168_private *tp, u8 addr, u16 clearmask, u16 setmask)
745
 {
746
-        void __iomem *ioaddr = tp->mmio_addr;
747
         u16 EphyValue;
748
 
749
-        EphyValue = rtl8168_ephy_read( ioaddr, addr );
750
+        EphyValue = rtl8168_ephy_read(tp, addr);
751
         EphyValue &= ~clearmask;
752
         EphyValue |= setmask;
753
-        rtl8168_ephy_write( ioaddr, addr, EphyValue);
754
+        rtl8168_ephy_write(tp, addr, EphyValue);
755
 }
756
 
757
 static void ClearPCIePhyBit(struct rtl8168_private *tp, u8 addr, u16 mask)
758
@@ -2578,7 +2481,6 @@
759
                            u8 multi_fun_sel_bit,
760
                            u32 addr)
761
 {
762
-        void __iomem *ioaddr = tp->mmio_addr;
763
         u32 cmd;
764
         int i;
765
         u32 value = 0;
766
@@ -2588,7 +2490,7 @@
767
         if (tp->mcfg != CFG_METHOD_20 && tp->mcfg != CFG_METHOD_23 &&
768
             tp->mcfg != CFG_METHOD_26 && tp->mcfg != CFG_METHOD_27 &&
769
             tp->mcfg != CFG_METHOD_28 && tp->mcfg != CFG_METHOD_31 &&
770
-            tp->mcfg != CFG_METHOD_32) {
771
+            tp->mcfg != CFG_METHOD_32 && tp->mcfg != CFG_METHOD_33) {
772
                 multi_fun_sel_bit = 0;
773
         }
774
 
775
@@ -2598,14 +2500,14 @@
776
 
777
         cmd |= multi_fun_sel_bit << 16;
778
 
779
-        RTL_W32(CSIAR, cmd);
780
+        RTL_W32(tp, CSIAR, cmd);
781
 
782
         for (i = 0; i < 10; i++) {
783
                 udelay(100);
784
 
785
                 /* Check if the RTL8168 has completed CSI read */
786
-                if (RTL_R32(CSIAR) & CSIAR_Flag) {
787
-                        value = (u32)RTL_R32(CSIDR);
788
+                if (RTL_R32(tp, CSIAR) & CSIAR_Flag) {
789
+                        value = (u32)RTL_R32(tp, CSIDR);
790
                         break;
791
                 }
792
         }
793
@@ -2621,16 +2523,15 @@
794
                             u32 addr,
795
                             u32 value)
796
 {
797
-        void __iomem *ioaddr = tp->mmio_addr;
798
         u32 cmd;
799
         int i;
800
 
801
-        RTL_W32(CSIDR, value);
802
+        RTL_W32(tp, CSIDR, value);
803
         cmd = CSIAR_Write | CSIAR_ByteEn << CSIAR_ByteEn_shift | (addr & CSIAR_Addr_Mask);
804
         if (tp->mcfg != CFG_METHOD_20 && tp->mcfg != CFG_METHOD_23 &&
805
             tp->mcfg != CFG_METHOD_26 && tp->mcfg != CFG_METHOD_27 &&
806
             tp->mcfg != CFG_METHOD_28 && tp->mcfg != CFG_METHOD_31 &&
807
-            tp->mcfg != CFG_METHOD_32) {
808
+            tp->mcfg != CFG_METHOD_32 && tp->mcfg != CFG_METHOD_33) {
809
                 multi_fun_sel_bit = 0;
810
         }
811
 
812
@@ -2640,13 +2541,13 @@
813
 
814
         cmd |= multi_fun_sel_bit << 16;
815
 
816
-        RTL_W32(CSIAR, cmd);
817
+        RTL_W32(tp, CSIAR, cmd);
818
 
819
         for (i = 0; i < 10; i++) {
820
                 udelay(100);
821
 
822
                 /* Check if the RTL8168 has completed CSI write */
823
-                if (!(RTL_R32(CSIAR) & CSIAR_Flag))
824
+                if (!(RTL_R32(tp, CSIAR) & CSIAR_Flag))
825
                         break;
826
         }
827
 
828
@@ -2662,7 +2563,7 @@
829
         if (tp->mcfg == CFG_METHOD_20)
830
                 multi_fun_sel_bit = 2;
831
         else if (tp->mcfg == CFG_METHOD_26 || tp->mcfg == CFG_METHOD_31 ||
832
-                 tp->mcfg == CFG_METHOD_32)
833
+                 tp->mcfg == CFG_METHOD_32 || tp->mcfg == CFG_METHOD_33)
834
                 multi_fun_sel_bit = 1;
835
         else
836
                 multi_fun_sel_bit = 0;
837
@@ -2680,7 +2581,7 @@
838
         if (tp->mcfg == CFG_METHOD_20)
839
                 multi_fun_sel_bit = 2;
840
         else if (tp->mcfg == CFG_METHOD_26 || tp->mcfg == CFG_METHOD_31 ||
841
-                 tp->mcfg == CFG_METHOD_32)
842
+                 tp->mcfg == CFG_METHOD_32 || tp->mcfg == CFG_METHOD_33)
843
                 multi_fun_sel_bit = 1;
844
         else
845
                 multi_fun_sel_bit = 0;
846
@@ -2695,7 +2596,8 @@
847
         u8 RetVal = 0;
848
 
849
         if (tp->mcfg == CFG_METHOD_20 || tp->mcfg == CFG_METHOD_26 ||
850
-            tp->mcfg == CFG_METHOD_31 || tp->mcfg == CFG_METHOD_32) {
851
+            tp->mcfg == CFG_METHOD_31 || tp->mcfg == CFG_METHOD_32 ||
852
+            tp->mcfg == CFG_METHOD_33) {
853
                 u32 TmpUlong;
854
                 u16 RegAlignAddr;
855
                 u8 ShiftByte;
856
@@ -2722,7 +2624,8 @@
857
                             u8 value)
858
 {
859
         if (tp->mcfg == CFG_METHOD_20 || tp->mcfg == CFG_METHOD_26 ||
860
-            tp->mcfg == CFG_METHOD_31 || tp->mcfg == CFG_METHOD_32) {
861
+            tp->mcfg == CFG_METHOD_31 || tp->mcfg == CFG_METHOD_32 ||
862
+            tp->mcfg == CFG_METHOD_33) {
863
                 u32 TmpUlong;
864
                 u16 RegAlignAddr;
865
                 u8 ShiftByte;
866
@@ -2783,6 +2686,7 @@
867
                 break;
868
         case CFG_METHOD_31:
869
         case CFG_METHOD_32:
870
+        case CFG_METHOD_33:
871
                 FunBit = 1;
872
                 for (i = 0; i < 8; i++) {
873
                         if (FunBit & multi_fun_sel_bit) {
874
@@ -2877,7 +2781,7 @@
875
         rtl8168_other_fun_dev_pci_setting(tp, 0x04, clearmask, setmask, multi_fun_sel_bit);
876
 }
877
 
878
-u32 rtl8168_eri_read_with_oob_base_address(void __iomem *ioaddr, int addr, int len, int type, const u32 base_address)
879
+u32 rtl8168_eri_read_with_oob_base_address(struct rtl8168_private *tp, int addr, int len, int type, const u32 base_address)
880
 {
881
         int i, val_shift, shift = 0;
882
         u32 value1 = 0, value2 = 0, mask;
883
@@ -2904,13 +2808,13 @@
884
                         eri_cmd |= (tmp << 20) & 0x00F00000;
885
                 }
886
 
887
-                RTL_W32(ERIAR, eri_cmd);
888
+                RTL_W32(tp, ERIAR, eri_cmd);
889
 
890
                 for (i = 0; i < 10; i++) {
891
                         udelay(100);
892
 
893
                         /* Check if the RTL8168 has completed ERI read */
894
-                        if (RTL_R32(ERIAR) & ERIAR_Flag)
895
+                        if (RTL_R32(tp, ERIAR) & ERIAR_Flag)
896
                                 break;
897
                 }
898
 
899
@@ -2919,7 +2823,7 @@
900
                 else if (len == 3)  mask = (0xFFFFFF << (val_shift * 8)) & 0xFFFFFFFF;
901
                 else            mask = (0xFFFFFFFF << (val_shift * 8)) & 0xFFFFFFFF;
902
 
903
-                value1 = RTL_R32(ERIDR) & mask;
904
+                value1 = RTL_R32(tp, ERIDR) & mask;
905
                 value2 |= (value1 >> val_shift * 8) << shift * 8;
906
 
907
                 if (len <= 4 - val_shift) {
908
@@ -2936,12 +2840,12 @@
909
         return value2;
910
 }
911
 
912
-u32 rtl8168_eri_read(void __iomem *ioaddr, int addr, int len, int type)
913
+u32 rtl8168_eri_read(struct rtl8168_private *tp, int addr, int len, int type)
914
 {
915
-        return rtl8168_eri_read_with_oob_base_address(ioaddr, addr, len, type, 0);
916
+        return rtl8168_eri_read_with_oob_base_address(tp, addr, len, type, 0);
917
 }
918
 
919
-int rtl8168_eri_write_with_oob_base_address(void __iomem *ioaddr, int addr, int len, u32 value, int type, const u32 base_address)
920
+int rtl8168_eri_write_with_oob_base_address(struct rtl8168_private *tp, int addr, int len, u32 value, int type, const u32 base_address)
921
 {
922
         int i, val_shift, shift = 0;
923
         u32 value1 = 0, mask;
924
@@ -2960,10 +2864,10 @@
925
                 else if (len == 3)  mask = (0xFFFFFF << (val_shift * 8)) & 0xFFFFFFFF;
926
                 else            mask = (0xFFFFFFFF << (val_shift * 8)) & 0xFFFFFFFF;
927
 
928
-                value1 = rtl8168_eri_read_with_oob_base_address(ioaddr, addr, 4, type, base_address) & ~mask;
929
+                value1 = rtl8168_eri_read_with_oob_base_address(tp, addr, 4, type, base_address) & ~mask;
930
                 value1 |= ((value << val_shift * 8) >> shift * 8);
931
 
932
-                RTL_W32(ERIDR, value1);
933
+                RTL_W32(tp, ERIDR, value1);
934
 
935
                 eri_cmd = ERIAR_Write |
936
                           transformed_base_address |
937
@@ -2978,13 +2882,13 @@
938
                         eri_cmd |= (tmp << 20) & 0x00F00000;
939
                 }
940
 
941
-                RTL_W32(ERIAR, eri_cmd);
942
+                RTL_W32(tp, ERIAR, eri_cmd);
943
 
944
                 for (i = 0; i < 10; i++) {
945
                         udelay(100);
946
 
947
                         /* Check if the RTL8168 has completed ERI write */
948
-                        if (!(RTL_R32(ERIAR) & ERIAR_Flag))
949
+                        if (!(RTL_R32(tp, ERIAR) & ERIAR_Flag))
950
                                 break;
951
                 }
952
 
953
@@ -3002,16 +2906,15 @@
954
         return 0;
955
 }
956
 
957
-int rtl8168_eri_write(void __iomem *ioaddr, int addr, int len, u32 value, int type)
958
+int rtl8168_eri_write(struct rtl8168_private *tp, int addr, int len, u32 value, int type)
959
 {
960
-        return rtl8168_eri_write_with_oob_base_address(ioaddr, addr, len, value, type, NO_BASE_ADDRESS);
961
+        return rtl8168_eri_write_with_oob_base_address(tp, addr, len, value, type, NO_BASE_ADDRESS);
962
 }
963
 
964
 static void
965
 rtl8168_enable_rxdvgate(struct net_device *dev)
966
 {
967
         struct rtl8168_private *tp = netdev_priv(dev);
968
-        void __iomem *ioaddr = tp->mmio_addr;
969
 
970
         switch (tp->mcfg) {
971
         case CFG_METHOD_21:
972
@@ -3026,7 +2929,8 @@
973
         case CFG_METHOD_30:
974
         case CFG_METHOD_31:
975
         case CFG_METHOD_32:
976
-                RTL_W8(0xF2, RTL_R8(0xF2) | BIT_3);
977
+        case CFG_METHOD_33:
978
+                RTL_W8(tp, 0xF2, RTL_R8(tp, 0xF2) | BIT_3);
979
                 mdelay(2);
980
                 break;
981
         }
982
@@ -3036,7 +2940,6 @@
983
 rtl8168_disable_rxdvgate(struct net_device *dev)
984
 {
985
         struct rtl8168_private *tp = netdev_priv(dev);
986
-        void __iomem *ioaddr = tp->mmio_addr;
987
 
988
         switch (tp->mcfg) {
989
         case CFG_METHOD_21:
990
@@ -3051,7 +2954,8 @@
991
         case CFG_METHOD_30:
992
         case CFG_METHOD_31:
993
         case CFG_METHOD_32:
994
-                RTL_W8(0xF2, RTL_R8(0xF2) & ~BIT_3);
995
+        case CFG_METHOD_33:
996
+                RTL_W8(tp, 0xF2, RTL_R8(tp, 0xF2) & ~BIT_3);
997
                 mdelay(2);
998
                 break;
999
         }
1000
@@ -3085,7 +2989,6 @@
1001
 rtl8168_is_phy_disable_mode_enabled(struct net_device *dev)
1002
 {
1003
         struct rtl8168_private *tp = netdev_priv(dev);
1004
-        void __iomem *ioaddr = tp->mmio_addr;
1005
         u8 phy_disable_mode_enabled = FALSE;
1006
 
1007
         switch (tp->HwSuppCheckPhyDisableModeVer) {
1008
@@ -3095,7 +2998,7 @@
1009
                 break;
1010
         case 2:
1011
         case 3:
1012
-                if (RTL_R8(0xF2) & BIT_5)
1013
+                if (RTL_R8(tp, 0xF2) & BIT_5)
1014
                         phy_disable_mode_enabled = TRUE;
1015
                 break;
1016
         }
1017
@@ -3124,7 +3027,6 @@
1018
 rtl8168_enable_phy_disable_mode(struct net_device *dev)
1019
 {
1020
         struct rtl8168_private *tp = netdev_priv(dev);
1021
-        void __iomem *ioaddr = tp->mmio_addr;
1022
 
1023
         switch (tp->HwSuppCheckPhyDisableModeVer) {
1024
         case 1:
1025
@@ -3132,7 +3034,7 @@
1026
                 break;
1027
         case 2:
1028
         case 3:
1029
-                RTL_W8(0xF2, RTL_R8(0xF2) | BIT_5);
1030
+                RTL_W8(tp, 0xF2, RTL_R8(tp, 0xF2) | BIT_5);
1031
                 break;
1032
         }
1033
 
1034
@@ -3143,7 +3045,6 @@
1035
 rtl8168_disable_phy_disable_mode(struct net_device *dev)
1036
 {
1037
         struct rtl8168_private *tp = netdev_priv(dev);
1038
-        void __iomem *ioaddr = tp->mmio_addr;
1039
 
1040
         switch (tp->HwSuppCheckPhyDisableModeVer) {
1041
         case 1:
1042
@@ -3151,7 +3052,7 @@
1043
                 break;
1044
         case 2:
1045
         case 3:
1046
-                RTL_W8(0xF2, RTL_R8(0xF2) & ~BIT_5);
1047
+                RTL_W8(tp, 0xF2, RTL_R8(tp, 0xF2) & ~BIT_5);
1048
                 break;
1049
         }
1050
 
1051
@@ -3164,7 +3065,6 @@
1052
 rtl8168_wait_txrx_fifo_empty(struct net_device *dev)
1053
 {
1054
         struct rtl8168_private *tp = netdev_priv(dev);
1055
-        void __iomem *ioaddr = tp->mmio_addr;
1056
         int i;
1057
 
1058
         switch (tp->mcfg) {
1059
@@ -3180,18 +3080,144 @@
1060
         case CFG_METHOD_30:
1061
         case CFG_METHOD_31:
1062
         case CFG_METHOD_32:
1063
+        case CFG_METHOD_33:
1064
                 for (i = 0; i < 10; i++) {
1065
                         udelay(100);
1066
-                        if (RTL_R32(TxConfig) & BIT_11)
1067
+                        if (RTL_R32(tp, TxConfig) & BIT_11)
1068
                                 break;
1069
                 }
1070
 
1071
                 for (i = 0; i < 10; i++) {
1072
                         udelay(100);
1073
-                        if ((RTL_R8(MCUCmd_reg) & (Txfifo_empty | Rxfifo_empty)) == (Txfifo_empty | Rxfifo_empty))
1074
+                        if ((RTL_R8(tp, MCUCmd_reg) & (Txfifo_empty | Rxfifo_empty)) == (Txfifo_empty | Rxfifo_empty))
1075
+                                break;
1076
+
1077
+                }
1078
+                break;
1079
+        }
1080
+}
1081
+
1082
+static void rtl8168_driver_start(struct rtl8168_private *tp)
1083
+{
1084
+        //change other device state to D0.
1085
+        switch (tp->mcfg) {
1086
+        case CFG_METHOD_23:
1087
+        case CFG_METHOD_27:
1088
+        case CFG_METHOD_28:
1089
+                rtl8168_set_dash_other_fun_dev_pci_cmd_register(tp, 0x07, 0x0E);
1090
+                rtl8168_set_dash_other_fun_dev_aspm_clkreq(tp, 3, 1, 0x0E);
1091
+                rtl8168_set_dash_other_fun_dev_state_change(tp, 0, 0x0E);
1092
+                break;
1093
+        case CFG_METHOD_31:
1094
+        case CFG_METHOD_32:
1095
+        case CFG_METHOD_33:
1096
+                rtl8168_set_dash_other_fun_dev_aspm_clkreq(tp, 2, 1, 0xED);
1097
+                rtl8168_set_dash_other_fun_dev_state_change(tp, 3, 0x78);
1098
+                if (tp->DASH) {
1099
+                        rtl8168_set_dash_other_fun_dev_state_change(tp, 0, 0x85);
1100
+                        rtl8168_set_dash_other_fun_dev_pci_cmd_register(tp, 0x07, 0x85);
1101
+                } else {
1102
+                        rtl8168_set_dash_other_fun_dev_state_change(tp, 3, 0x85);
1103
+                }
1104
+                break;
1105
+        }
1106
+
1107
+        if (!tp->DASH)
1108
+                return;
1109
+
1110
+        if (HW_DASH_SUPPORT_TYPE_2(tp) || HW_DASH_SUPPORT_TYPE_3(tp)) {
1111
+                int timeout;
1112
+                u32 tmp_value;
1113
+
1114
+                rtl8168_ocp_write(tp, 0x180, 1, OOB_CMD_DRIVER_START);
1115
+                tmp_value = rtl8168_ocp_read(tp, 0x30, 1);
1116
+                tmp_value |= BIT_0;
1117
+                rtl8168_ocp_write(tp, 0x30, 1, tmp_value);
1118
+
1119
+                for (timeout = 0; timeout < 10; timeout++) {
1120
+                        mdelay(10);
1121
+                        if (rtl8168_ocp_read(tp, 0x124, 1) & BIT_0)
1122
+                                break;
1123
+                }
1124
+        } else {
1125
+                int timeout;
1126
+                u32 reg;
1127
+
1128
+                if (tp->mcfg == CFG_METHOD_13) {
1129
+                        RTL_W8(tp, TwiCmdReg, RTL_R8(tp, TwiCmdReg) | ( BIT_7 ));
1130
+                }
1131
+
1132
+                rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
1133
+
1134
+                if (tp->mcfg == CFG_METHOD_13)
1135
+                        reg = 0xB8;
1136
+                else
1137
+                        reg = 0x10;
1138
+
1139
+                for (timeout = 0; timeout < 10; timeout++) {
1140
+                        mdelay(10);
1141
+                        if (rtl8168_ocp_read(tp, reg, 2) & BIT_11)
1142
+                                break;
1143
+                }
1144
+        }
1145
+}
1146
+
1147
+static void rtl8168_driver_stop(struct rtl8168_private *tp)
1148
+{
1149
+        if (!tp->DASH)
1150
+                goto update_device_state;
1151
+
1152
+        if (HW_DASH_SUPPORT_TYPE_2(tp) || HW_DASH_SUPPORT_TYPE_3(tp)) {
1153
+                struct net_device *dev = tp->dev;
1154
+                int timeout;
1155
+                u32 tmp_value;
1156
+
1157
+                rtl8168_dash2_disable_txrx(dev);
1158
+
1159
+                rtl8168_ocp_write(tp, 0x180, 1, OOB_CMD_DRIVER_STOP);
1160
+                tmp_value = rtl8168_ocp_read(tp, 0x30, 1);
1161
+                tmp_value |= BIT_0;
1162
+                rtl8168_ocp_write(tp, 0x30, 1, tmp_value);
1163
+
1164
+                for (timeout = 0; timeout < 10; timeout++) {
1165
+                        mdelay(10);
1166
+                        if (!(rtl8168_ocp_read(tp, 0x124, 1) & BIT_0))
1167
                                 break;
1168
+                }
1169
+        } else {
1170
+                int timeout;
1171
+                u32 reg;
1172
+
1173
+                rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1174
 
1175
+                if (tp->mcfg == CFG_METHOD_13)
1176
+                        reg = 0xB8;
1177
+                else
1178
+                        reg = 0x10;
1179
+
1180
+                for (timeout = 0; timeout < 10; timeout++) {
1181
+                        mdelay(10);
1182
+                        if ((rtl8168_ocp_read(tp, reg, 2) & BIT_11) == 0)
1183
+                                break;
1184
                 }
1185
+
1186
+                if (tp->mcfg == CFG_METHOD_13) {
1187
+                        RTL_W8(tp, TwiCmdReg, RTL_R8(tp, TwiCmdReg) & ~( BIT_7 ));
1188
+                }
1189
+        }
1190
+
1191
+update_device_state:
1192
+        //change other device state to D3.
1193
+        switch (tp->mcfg) {
1194
+        case CFG_METHOD_23:
1195
+        case CFG_METHOD_27:
1196
+        case CFG_METHOD_28:
1197
+                rtl8168_set_dash_other_fun_dev_state_change(tp, 3, 0x0E);
1198
+                break;
1199
+        case CFG_METHOD_31:
1200
+        case CFG_METHOD_32:
1201
+        case CFG_METHOD_33:
1202
+                rtl8168_set_dash_other_fun_dev_state_change(tp, 3, 0xFD);
1203
                 break;
1204
         }
1205
 }
1206
@@ -3199,93 +3225,93 @@
1207
 #ifdef ENABLE_DASH_SUPPORT
1208
 
1209
 inline void
1210
-rtl8168_enable_dash2_interrupt(struct rtl8168_private *tp, void __iomem *ioaddr)
1211
+rtl8168_enable_dash2_interrupt(struct rtl8168_private *tp)
1212
 {
1213
         if (!tp->DASH) return;
1214
 
1215
         if (HW_DASH_SUPPORT_TYPE_2(tp) || HW_DASH_SUPPORT_TYPE_3(tp)) {
1216
-                RTL_CMAC_W8(CMAC_IBIMR0, ( ISRIMR_DASH_TYPE2_ROK | ISRIMR_DASH_TYPE2_TOK | ISRIMR_DASH_TYPE2_TDU | ISRIMR_DASH_TYPE2_RDU | ISRIMR_DASH_TYPE2_RX_DISABLE_IDLE ));
1217
+                RTL_CMAC_W8(tp, CMAC_IBIMR0, ( ISRIMR_DASH_TYPE2_ROK | ISRIMR_DASH_TYPE2_TOK | ISRIMR_DASH_TYPE2_TDU | ISRIMR_DASH_TYPE2_RDU | ISRIMR_DASH_TYPE2_RX_DISABLE_IDLE ));
1218
         }
1219
 }
1220
 
1221
 static inline void
1222
-rtl8168_disable_dash2_interrupt(struct rtl8168_private *tp, void __iomem *ioaddr)
1223
+rtl8168_disable_dash2_interrupt(struct rtl8168_private *tp)
1224
 {
1225
         if (!tp->DASH) return;
1226
 
1227
         if (HW_DASH_SUPPORT_TYPE_2(tp) || HW_DASH_SUPPORT_TYPE_3(tp)) {
1228
-                RTL_CMAC_W8(CMAC_IBIMR0, 0);
1229
+                RTL_CMAC_W8(tp, CMAC_IBIMR0, 0);
1230
         }
1231
 }
1232
 #endif
1233
 
1234
 static inline void
1235
-rtl8168_enable_hw_interrupt(struct rtl8168_private *tp, void __iomem *ioaddr)
1236
+rtl8168_enable_hw_interrupt(struct rtl8168_private *tp)
1237
 {
1238
-        RTL_W16(IntrMask, tp->intr_mask);
1239
+        RTL_W16(tp, IntrMask, tp->intr_mask);
1240
 
1241
 #ifdef ENABLE_DASH_SUPPORT
1242
         if (tp->DASH)
1243
-                rtl8168_enable_dash2_interrupt(tp, ioaddr);
1244
+                rtl8168_enable_dash2_interrupt(tp);
1245
 #endif
1246
 }
1247
 
1248
 static inline void
1249
-rtl8168_disable_hw_interrupt(struct rtl8168_private *tp, void __iomem *ioaddr)
1250
+rtl8168_disable_hw_interrupt(struct rtl8168_private *tp)
1251
 {
1252
-        RTL_W16(IntrMask, 0x0000);
1253
+        RTL_W16(tp, IntrMask, 0x0000);
1254
 
1255
 #ifdef ENABLE_DASH_SUPPORT
1256
         if (tp->DASH)
1257
-                rtl8168_disable_dash2_interrupt(tp, ioaddr);
1258
+                rtl8168_disable_dash2_interrupt(tp);
1259
 #endif
1260
 }
1261
 
1262
 
1263
 static inline void
1264
-rtl8168_switch_to_hw_interrupt(struct rtl8168_private *tp, void __iomem *ioaddr)
1265
+rtl8168_switch_to_hw_interrupt(struct rtl8168_private *tp)
1266
 {
1267
-        RTL_W32(TimeInt0, 0x0000);
1268
+        RTL_W32(tp, TimeInt0, 0x0000);
1269
 
1270
-        rtl8168_enable_hw_interrupt(tp, ioaddr);
1271
+        rtl8168_enable_hw_interrupt(tp);
1272
 }
1273
 
1274
 static inline void
1275
-rtl8168_switch_to_timer_interrupt(struct rtl8168_private *tp, void __iomem *ioaddr)
1276
+rtl8168_switch_to_timer_interrupt(struct rtl8168_private *tp)
1277
 {
1278
         if (tp->use_timer_interrrupt) {
1279
-                RTL_W32(TimeInt0, timer_count);
1280
-                RTL_W32(TCTR, timer_count);
1281
-                RTL_W16(IntrMask, tp->timer_intr_mask);
1282
+                RTL_W32(tp, TimeInt0, timer_count);
1283
+                RTL_W32(tp, TCTR, timer_count);
1284
+                RTL_W16(tp, IntrMask, tp->timer_intr_mask);
1285
 
1286
 #ifdef ENABLE_DASH_SUPPORT
1287
                 if (tp->DASH)
1288
-                        rtl8168_enable_dash2_interrupt(tp, ioaddr);
1289
+                        rtl8168_enable_dash2_interrupt(tp);
1290
 #endif
1291
         } else {
1292
-                rtl8168_switch_to_hw_interrupt(tp, ioaddr);
1293
+                rtl8168_switch_to_hw_interrupt(tp);
1294
         }
1295
 }
1296
 
1297
 static void
1298
-rtl8168_irq_mask_and_ack(struct rtl8168_private *tp, void __iomem *ioaddr)
1299
+rtl8168_irq_mask_and_ack(struct rtl8168_private *tp)
1300
 {
1301
-        rtl8168_disable_hw_interrupt(tp, ioaddr);
1302
+        rtl8168_disable_hw_interrupt(tp);
1303
 #ifdef ENABLE_DASH_SUPPORT
1304
         if (tp->DASH) {
1305
                 if (tp->dash_printer_enabled) {
1306
-                        RTL_W16(IntrStatus, RTL_R16(IntrStatus) &
1307
+                        RTL_W16(tp, IntrStatus, RTL_R16(tp, IntrStatus) &
1308
                                 ~(ISRIMR_DASH_INTR_EN | ISRIMR_DASH_INTR_CMAC_RESET));
1309
                 } else {
1310
                         if (HW_DASH_SUPPORT_TYPE_2(tp) || HW_DASH_SUPPORT_TYPE_3(tp)) {
1311
-                                RTL_CMAC_W8(CMAC_IBISR0, RTL_CMAC_R8(CMAC_IBISR0));
1312
+                                RTL_CMAC_W8(tp, CMAC_IBISR0, RTL_CMAC_R8(tp, CMAC_IBISR0));
1313
                         }
1314
                 }
1315
         } else {
1316
-                RTL_W16(IntrStatus, RTL_R16(IntrStatus));
1317
+                RTL_W16(tp, IntrStatus, RTL_R16(tp, IntrStatus));
1318
         }
1319
 #else
1320
-        RTL_W16(IntrStatus, RTL_R16(IntrStatus));
1321
+        RTL_W16(tp, IntrStatus, RTL_R16(tp, IntrStatus));
1322
 #endif
1323
 }
1324
 
1325
@@ -3293,10 +3319,9 @@
1326
 rtl8168_nic_reset(struct net_device *dev)
1327
 {
1328
         struct rtl8168_private *tp = netdev_priv(dev);
1329
-        void __iomem *ioaddr = tp->mmio_addr;
1330
         int i;
1331
 
1332
-        RTL_W32(RxConfig, (RX_DMA_BURST << RxCfgDMAShift));
1333
+        RTL_W32(tp, RxConfig, (RX_DMA_BURST << RxCfgDMAShift));
1334
 
1335
         rtl8168_enable_rxdvgate(dev);
1336
 
1337
@@ -3317,14 +3342,14 @@
1338
         case CFG_METHOD_10:
1339
         case CFG_METHOD_14:
1340
         case CFG_METHOD_15:
1341
-                RTL_W8(ChipCmd, StopReq | CmdRxEnb | CmdTxEnb);
1342
+                RTL_W8(tp, ChipCmd, StopReq | CmdRxEnb | CmdTxEnb);
1343
                 udelay(100);
1344
                 break;
1345
         case CFG_METHOD_11:
1346
         case CFG_METHOD_12:
1347
         case CFG_METHOD_13:
1348
                 for (i = 0; i < 2000; i++) {
1349
-                        if (!(RTL_R8(TxPoll) & NPQ)) break;
1350
+                        if (!(RTL_R8(tp, TxPoll) & NPQ)) break;
1351
                         udelay(100);
1352
                 }
1353
                 break;
1354
@@ -3340,6 +3365,7 @@
1355
         case CFG_METHOD_30:
1356
         case CFG_METHOD_31:
1357
         case CFG_METHOD_32:
1358
+        case CFG_METHOD_33:
1359
                 mdelay(2);
1360
                 break;
1361
         default:
1362
@@ -3348,12 +3374,12 @@
1363
         }
1364
 
1365
         /* Soft reset the chip. */
1366
-        RTL_W8(ChipCmd, CmdReset);
1367
+        RTL_W8(tp, ChipCmd, CmdReset);
1368
 
1369
         /* Check that the chip has finished the reset. */
1370
         for (i = 100; i > 0; i--) {
1371
                 udelay(100);
1372
-                if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1373
+                if ((RTL_R8(tp, ChipCmd) & CmdReset) == 0)
1374
                         break;
1375
         }
1376
 
1377
@@ -3383,9 +3409,8 @@
1378
 rtl8168_hw_clear_timer_int(struct net_device *dev)
1379
 {
1380
         struct rtl8168_private *tp = netdev_priv(dev);
1381
-        void __iomem *ioaddr = tp->mmio_addr;
1382
 
1383
-        RTL_W32(TimeInt0, 0x0000);
1384
+        RTL_W32(tp, TimeInt0, 0x0000);
1385
 
1386
         switch (tp->mcfg) {
1387
         case CFG_METHOD_4:
1388
@@ -3393,7 +3418,7 @@
1389
         case CFG_METHOD_6:
1390
         case CFG_METHOD_7:
1391
         case CFG_METHOD_8:
1392
-                RTL_W32(TimeInt1, 0x0000);
1393
+                RTL_W32(tp, TimeInt1, 0x0000);
1394
                 break;
1395
         case CFG_METHOD_9:
1396
         case CFG_METHOD_10:
1397
@@ -3419,9 +3444,10 @@
1398
         case CFG_METHOD_30:
1399
         case CFG_METHOD_31:
1400
         case CFG_METHOD_32:
1401
-                RTL_W32(TimeInt1, 0x0000);
1402
-                RTL_W32(TimeInt2, 0x0000);
1403
-                RTL_W32(TimeInt3, 0x0000);
1404
+        case CFG_METHOD_33:
1405
+                RTL_W32(tp, TimeInt1, 0x0000);
1406
+                RTL_W32(tp, TimeInt2, 0x0000);
1407
+                RTL_W32(tp, TimeInt3, 0x0000);
1408
                 break;
1409
         }
1410
 }
1411
@@ -3430,10 +3456,9 @@
1412
 rtl8168_hw_reset(struct net_device *dev)
1413
 {
1414
         struct rtl8168_private *tp = netdev_priv(dev);
1415
-        void __iomem *ioaddr = tp->mmio_addr;
1416
 
1417
         /* Disable interrupts */
1418
-        rtl8168_irq_mask_and_ack(tp, ioaddr);
1419
+        rtl8168_irq_mask_and_ack(tp);
1420
 
1421
         rtl8168_hw_clear_timer_int(dev);
1422
 
1423
@@ -3442,7 +3467,7 @@
1424
 
1425
 static void rtl8168_mac_loopback_test(struct rtl8168_private *tp)
1426
 {
1427
-        void __iomem *ioaddr = tp->mmio_addr;
1428
+        struct pci_dev *pdev = tp->pci_dev;
1429
         struct net_device *dev = tp->dev;
1430
         struct sk_buff *skb, *rx_skb;
1431
         dma_addr_t mapping;
1432
@@ -3463,7 +3488,7 @@
1433
         txd = tp->TxDescArray;
1434
         rxd = tp->RxDescArray;
1435
         rx_skb = tp->Rx_skbuff[0];
1436
-        RTL_W32(TxConfig, (RTL_R32(TxConfig) & ~0x00060000) | 0x00020000);
1437
+        RTL_W32(tp, TxConfig, (RTL_R32(tp, TxConfig) & ~0x00060000) | 0x00020000);
1438
 
1439
         do {
1440
                 skb = dev_alloc_skb(len + RTK_RX_ALIGN);
1441
@@ -3477,22 +3502,22 @@
1442
         memcpy(skb_put(skb, sizeof(type)), &type, sizeof(type));
1443
         tmpAddr = skb_put(skb, len - 14);
1444
 
1445
-        mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
1446
-        pci_dma_sync_single_for_cpu(tp->pci_dev, le64_to_cpu(mapping),
1447
-                                    len, PCI_DMA_TODEVICE);
1448
+        mapping = dma_map_single(&tp->pci_dev->dev, skb->data, len, DMA_TO_DEVICE);
1449
+        dma_sync_single_for_cpu(&tp->pci_dev->dev, le64_to_cpu(mapping),
1450
+                                len, DMA_TO_DEVICE);
1451
         txd->addr = cpu_to_le64(mapping);
1452
         txd->opts2 = 0;
1453
         while (1) {
1454
                 memset(tmpAddr, pattern++, len - 14);
1455
                 pci_dma_sync_single_for_device(tp->pci_dev,
1456
                                                le64_to_cpu(mapping),
1457
-                                               len, PCI_DMA_TODEVICE);
1458
+                                               len, DMA_TO_DEVICE);
1459
                 txd->opts1 = cpu_to_le32(DescOwn | FirstFrag | LastFrag | len);
1460
 
1461
-                RTL_W32(RxConfig, RTL_R32(RxConfig)  | AcceptMyPhys);
1462
+                RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig)  | AcceptMyPhys);
1463
 
1464
                 smp_wmb();
1465
-                RTL_W8(TxPoll, NPQ);    /* set polling bit */
1466
+                RTL_W8(tp, TxPoll, NPQ);    /* set polling bit */
1467
 
1468
                 for (i = 0; i < 50; i++) {
1469
                         udelay(200);
1470
@@ -3501,18 +3526,18 @@
1471
                                 break;
1472
                 }
1473
 
1474
-                RTL_W32(RxConfig, RTL_R32(RxConfig) & ~(AcceptErr | AcceptRunt | AcceptBroadcast | AcceptMulticast | AcceptMyPhys |  AcceptAllPhys));
1475
+                RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~(AcceptErr | AcceptRunt | AcceptBroadcast | AcceptMulticast | AcceptMyPhys |  AcceptAllPhys));
1476
 
1477
                 rx_len = rx_cmd & 0x3FFF;
1478
                 rx_len -= 4;
1479
                 rxd->opts1 = cpu_to_le32(DescOwn | tp->rx_buf_sz);
1480
 
1481
-                pci_dma_sync_single_for_cpu(tp->pci_dev, le64_to_cpu(mapping), len, PCI_DMA_TODEVICE);
1482
+                dma_sync_single_for_cpu(&tp->pci_dev->dev, le64_to_cpu(mapping), len, DMA_TO_DEVICE);
1483
 
1484
                 if (rx_len == len) {
1485
-                        pci_dma_sync_single_for_cpu(tp->pci_dev, le64_to_cpu(rxd->addr), tp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1486
+                        dma_sync_single_for_cpu(&tp->pci_dev->dev, le64_to_cpu(rxd->addr), tp->rx_buf_sz, DMA_FROM_DEVICE);
1487
                         i = memcmp(skb->data, rx_skb->data, rx_len);
1488
-                        pci_dma_sync_single_for_device(tp->pci_dev, le64_to_cpu(rxd->addr), tp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1489
+                        pci_dma_sync_single_for_device(tp->pci_dev, le64_to_cpu(rxd->addr), tp->rx_buf_sz, DMA_FROM_DEVICE);
1490
                         if (i == 0) {
1491
 //              dev_printk(KERN_INFO, &tp->pci_dev->dev, "loopback test finished\n",rx_len,len);
1492
                                 break;
1493
@@ -3521,17 +3546,17 @@
1494
 
1495
                 rtl8168_hw_reset(dev);
1496
                 rtl8168_disable_rxdvgate(dev);
1497
-                RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
1498
+                RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
1499
         }
1500
         tp->dirty_tx++;
1501
         tp->dirty_rx++;
1502
         tp->cur_tx++;
1503
         tp->cur_rx++;
1504
-        pci_unmap_single(tp->pci_dev, le64_to_cpu(mapping),
1505
-                         len, PCI_DMA_TODEVICE);
1506
-        RTL_W32(TxConfig, RTL_R32(TxConfig) & ~0x00060000);
1507
+        dma_unmap_single(&pdev->dev, le64_to_cpu(mapping),
1508
+                         len, DMA_TO_DEVICE);
1509
+        RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) & ~0x00060000);
1510
         dev_kfree_skb_any(skb);
1511
-        RTL_W16(IntrStatus, 0xFFBF);
1512
+        RTL_W16(tp, IntrStatus, 0xFFBF);
1513
 }
1514
 
1515
 static unsigned int
1516
@@ -3550,10 +3575,9 @@
1517
 rtl8168_xmii_link_ok(struct net_device *dev)
1518
 {
1519
         struct rtl8168_private *tp = netdev_priv(dev);
1520
-        void __iomem *ioaddr = tp->mmio_addr;
1521
         unsigned int retval;
1522
 
1523
-        retval = (RTL_R8(PHYstatus) & LinkStatus) ? 1 : 0;
1524
+        retval = (RTL_R8(tp, PHYstatus) & LinkStatus) ? 1 : 0;
1525
 
1526
         return retval;
1527
 }
1528
@@ -3593,8 +3617,7 @@
1529
 rtl8168dp_10mbps_gphy_para(struct net_device *dev)
1530
 {
1531
         struct rtl8168_private *tp = netdev_priv(dev);
1532
-        void __iomem *ioaddr = tp->mmio_addr;
1533
-        u8 status = RTL_R8(PHYstatus);
1534
+        u8 status = RTL_R8(tp, PHYstatus);
1535
 
1536
         if ((status & LinkStatus) && (status & _10bps)) {
1537
                 rtl8168_mdio_write(tp, 0x1f, 0x0000);
1538
@@ -3616,7 +3639,6 @@
1539
 static void
1540
 rtl8168_issue_offset_99_event(struct rtl8168_private *tp)
1541
 {
1542
-        void __iomem *ioaddr = tp->mmio_addr;
1543
         u32 csi_tmp;
1544
 
1545
         switch (tp->mcfg) {
1546
@@ -3629,21 +3651,22 @@
1547
         case CFG_METHOD_28:
1548
                 if (tp->mcfg == CFG_METHOD_24 || tp->mcfg == CFG_METHOD_25 ||
1549
                     tp->mcfg == CFG_METHOD_27 || tp->mcfg == CFG_METHOD_28) {
1550
-                        rtl8168_eri_write(ioaddr, 0x3FC, 4, 0x00000000, ERIAR_ExGMAC);
1551
+                        rtl8168_eri_write(tp, 0x3FC, 4, 0x00000000, ERIAR_ExGMAC);
1552
                 } else {
1553
-                        rtl8168_eri_write(ioaddr, 0x3FC, 4, 0x083C083C, ERIAR_ExGMAC);
1554
+                        rtl8168_eri_write(tp, 0x3FC, 4, 0x083C083C, ERIAR_ExGMAC);
1555
                 }
1556
-                csi_tmp = rtl8168_eri_read(ioaddr, 0x3F8, 1, ERIAR_ExGMAC);
1557
+                csi_tmp = rtl8168_eri_read(tp, 0x3F8, 1, ERIAR_ExGMAC);
1558
                 csi_tmp |= BIT_0;
1559
-                rtl8168_eri_write(ioaddr, 0x3F8, 1, csi_tmp, ERIAR_ExGMAC);
1560
+                rtl8168_eri_write(tp, 0x3F8, 1, csi_tmp, ERIAR_ExGMAC);
1561
                 break;
1562
         case CFG_METHOD_29:
1563
         case CFG_METHOD_30:
1564
         case CFG_METHOD_31:
1565
         case CFG_METHOD_32:
1566
-                csi_tmp = rtl8168_eri_read(ioaddr, 0x1EA, 1, ERIAR_ExGMAC);
1567
+        case CFG_METHOD_33:
1568
+                csi_tmp = rtl8168_eri_read(tp, 0x1EA, 1, ERIAR_ExGMAC);
1569
                 csi_tmp |= BIT_0;
1570
-                rtl8168_eri_write(ioaddr, 0x1EA, 1, csi_tmp, ERIAR_ExGMAC);
1571
+                rtl8168_eri_write(tp, 0x1EA, 1, csi_tmp, ERIAR_ExGMAC);
1572
                 break;
1573
         }
1574
 }
1575
@@ -3652,17 +3675,15 @@
1576
 static void
1577
 NICChkTypeEnableDashInterrupt(struct rtl8168_private *tp)
1578
 {
1579
-        void __iomem *ioaddr = tp->mmio_addr;
1580
-
1581
         if (tp->DASH) {
1582
                 //
1583
                 // even disconnected, enable 3 dash interrupt mask bits for in-band/out-band communication
1584
                 //
1585
                 if (HW_DASH_SUPPORT_TYPE_2(tp) || HW_DASH_SUPPORT_TYPE_3(tp)) {
1586
-                        rtl8168_enable_dash2_interrupt(tp, ioaddr);
1587
-                        RTL_W16(IntrMask, (ISRIMR_DASH_INTR_EN | ISRIMR_DASH_INTR_CMAC_RESET));
1588
+                        rtl8168_enable_dash2_interrupt(tp);
1589
+                        RTL_W16(tp, IntrMask, (ISRIMR_DASH_INTR_EN | ISRIMR_DASH_INTR_CMAC_RESET));
1590
                 } else {
1591
-                        RTL_W16(IntrMask, (ISRIMR_DP_DASH_OK | ISRIMR_DP_HOST_OK | ISRIMR_DP_REQSYS_OK));
1592
+                        RTL_W16(tp, IntrMask, (ISRIMR_DP_DASH_OK | ISRIMR_DP_HOST_OK | ISRIMR_DP_REQSYS_OK));
1593
                 }
1594
         }
1595
 }
1596
@@ -3672,7 +3693,6 @@
1597
 rtl8168_check_link_status(struct net_device *dev)
1598
 {
1599
         struct rtl8168_private *tp = netdev_priv(dev);
1600
-        void __iomem *ioaddr = tp->mmio_addr;
1601
         int link_status_on;
1602
 
1603
 #ifdef ENABLE_FIBER_SUPPORT
1604
@@ -3693,76 +3713,78 @@
1605
                         rtl8168_hw_config(dev);
1606
 
1607
                         if (tp->mcfg == CFG_METHOD_18 || tp->mcfg == CFG_METHOD_19 || tp->mcfg == CFG_METHOD_20) {
1608
-                                if (RTL_R8(PHYstatus) & _1000bpsF) {
1609
-                                        rtl8168_eri_write(ioaddr, 0x1bc, 4, 0x00000011, ERIAR_ExGMAC);
1610
-                                        rtl8168_eri_write(ioaddr, 0x1dc, 4, 0x0000001f, ERIAR_ExGMAC);
1611
-                                } else if (RTL_R8(PHYstatus) & _100bps) {
1612
-                                        rtl8168_eri_write(ioaddr, 0x1bc, 4, 0x0000001f, ERIAR_ExGMAC);
1613
-                                        rtl8168_eri_write(ioaddr, 0x1dc, 4, 0x0000001f, ERIAR_ExGMAC);
1614
+                                if (RTL_R8(tp, PHYstatus) & _1000bpsF) {
1615
+                                        rtl8168_eri_write(tp, 0x1bc, 4, 0x00000011, ERIAR_ExGMAC);
1616
+                                        rtl8168_eri_write(tp, 0x1dc, 4, 0x0000001f, ERIAR_ExGMAC);
1617
+                                } else if (RTL_R8(tp, PHYstatus) & _100bps) {
1618
+                                        rtl8168_eri_write(tp, 0x1bc, 4, 0x0000001f, ERIAR_ExGMAC);
1619
+                                        rtl8168_eri_write(tp, 0x1dc, 4, 0x0000001f, ERIAR_ExGMAC);
1620
                                 } else {
1621
-                                        rtl8168_eri_write(ioaddr, 0x1bc, 4, 0x0000001f, ERIAR_ExGMAC);
1622
-                                        rtl8168_eri_write(ioaddr, 0x1dc, 4, 0x0000002d, ERIAR_ExGMAC);
1623
+                                        rtl8168_eri_write(tp, 0x1bc, 4, 0x0000001f, ERIAR_ExGMAC);
1624
+                                        rtl8168_eri_write(tp, 0x1dc, 4, 0x0000002d, ERIAR_ExGMAC);
1625
                                 }
1626
                         } else if ((tp->mcfg == CFG_METHOD_16 || tp->mcfg == CFG_METHOD_17) && netif_running(dev)) {
1627
-                                if (tp->mcfg == CFG_METHOD_16 && (RTL_R8(PHYstatus) & _10bps)) {
1628
-                                        RTL_W32(RxConfig, RTL_R32(RxConfig) | AcceptAllPhys);
1629
+                                if (tp->mcfg == CFG_METHOD_16 && (RTL_R8(tp, PHYstatus) & _10bps)) {
1630
+                                        RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) | AcceptAllPhys);
1631
                                 } else if (tp->mcfg == CFG_METHOD_17) {
1632
-                                        if (RTL_R8(PHYstatus) & _1000bpsF) {
1633
-                                                rtl8168_eri_write(ioaddr, 0x1bc, 4, 0x00000011, ERIAR_ExGMAC);
1634
-                                                rtl8168_eri_write(ioaddr, 0x1dc, 4, 0x00000005, ERIAR_ExGMAC);
1635
-                                        } else if (RTL_R8(PHYstatus) & _100bps) {
1636
-                                                rtl8168_eri_write(ioaddr, 0x1bc, 4, 0x0000001f, ERIAR_ExGMAC);
1637
-                                                rtl8168_eri_write(ioaddr, 0x1dc, 4, 0x00000005, ERIAR_ExGMAC);
1638
+                                        if (RTL_R8(tp, PHYstatus) & _1000bpsF) {
1639
+                                                rtl8168_eri_write(tp, 0x1bc, 4, 0x00000011, ERIAR_ExGMAC);
1640
+                                                rtl8168_eri_write(tp, 0x1dc, 4, 0x00000005, ERIAR_ExGMAC);
1641
+                                        } else if (RTL_R8(tp, PHYstatus) & _100bps) {
1642
+                                                rtl8168_eri_write(tp, 0x1bc, 4, 0x0000001f, ERIAR_ExGMAC);
1643
+                                                rtl8168_eri_write(tp, 0x1dc, 4, 0x00000005, ERIAR_ExGMAC);
1644
                                         } else {
1645
-                                                rtl8168_eri_write(ioaddr, 0x1bc, 4, 0x0000001f, ERIAR_ExGMAC);
1646
-                                                rtl8168_eri_write(ioaddr, 0x1dc, 4, 0x0000003f, ERIAR_ExGMAC);
1647
+                                                rtl8168_eri_write(tp, 0x1bc, 4, 0x0000001f, ERIAR_ExGMAC);
1648
+                                                rtl8168_eri_write(tp, 0x1dc, 4, 0x0000003f, ERIAR_ExGMAC);
1649
                                         }
1650
                                 }
1651
-                        } else if ((tp->mcfg == CFG_METHOD_14 || tp->mcfg == CFG_METHOD_15) && eee_enable ==1) {
1652
+                        } else if ((tp->mcfg == CFG_METHOD_14 || tp->mcfg == CFG_METHOD_15) && tp->eee_enabled == 1) {
1653
                                 /*Full -Duplex  mode*/
1654
-                                if (RTL_R8(PHYstatus)&FullDup) {
1655
+                                if (RTL_R8(tp, PHYstatus)&FullDup) {
1656
                                         rtl8168_mdio_write(tp, 0x1F, 0x0006);
1657
                                         rtl8168_mdio_write(tp, 0x00, 0x5a30);
1658
                                         rtl8168_mdio_write(tp, 0x1F, 0x0000);
1659
-                                        if (RTL_R8(PHYstatus) & (_10bps | _100bps))
1660
-                                                RTL_W32(TxConfig, (RTL_R32(TxConfig) & ~BIT_19) | BIT_25);
1661
+                                        if (RTL_R8(tp, PHYstatus) & (_10bps | _100bps))
1662
+                                                RTL_W32(tp, TxConfig, (RTL_R32(tp, TxConfig) & ~BIT_19) | BIT_25);
1663
 
1664
                                 } else {
1665
                                         rtl8168_mdio_write(tp, 0x1F, 0x0006);
1666
                                         rtl8168_mdio_write(tp, 0x00, 0x5a00);
1667
                                         rtl8168_mdio_write(tp, 0x1F, 0x0000);
1668
-                                        if (RTL_R8(PHYstatus) & (_10bps | _100bps))
1669
-                                                RTL_W32(TxConfig, (RTL_R32(TxConfig) & ~BIT_19) | (InterFrameGap << TxInterFrameGapShift));
1670
+                                        if (RTL_R8(tp, PHYstatus) & (_10bps | _100bps))
1671
+                                                RTL_W32(tp, TxConfig, (RTL_R32(tp, TxConfig) & ~BIT_19) | (InterFrameGap << TxInterFrameGapShift));
1672
                                 }
1673
                         } else if ((tp->mcfg == CFG_METHOD_21 || tp->mcfg == CFG_METHOD_22 ||
1674
                                     tp->mcfg == CFG_METHOD_23 || tp->mcfg == CFG_METHOD_24 ||
1675
                                     tp->mcfg == CFG_METHOD_25 || tp->mcfg == CFG_METHOD_26 ||
1676
                                     tp->mcfg == CFG_METHOD_27 || tp->mcfg == CFG_METHOD_28 ||
1677
                                     tp->mcfg == CFG_METHOD_29 || tp->mcfg == CFG_METHOD_30 ||
1678
-                                    tp->mcfg == CFG_METHOD_31 || tp->mcfg == CFG_METHOD_32) &&
1679
-                                   netif_running(dev)) {
1680
-                                if (RTL_R8(PHYstatus)&FullDup)
1681
-                                        RTL_W32(TxConfig, (RTL_R32(TxConfig) | (BIT_24 | BIT_25)) & ~BIT_19);
1682
+                                    tp->mcfg == CFG_METHOD_31 || tp->mcfg == CFG_METHOD_32 ||
1683
+                                    tp->mcfg == CFG_METHOD_33) && netif_running(dev)) {
1684
+                                if (RTL_R8(tp, PHYstatus)&FullDup)
1685
+                                        RTL_W32(tp, TxConfig, (RTL_R32(tp, TxConfig) | (BIT_24 | BIT_25)) & ~BIT_19);
1686
                                 else
1687
-                                        RTL_W32(TxConfig, (RTL_R32(TxConfig) | BIT_25) & ~(BIT_19 | BIT_24));
1688
+                                        RTL_W32(tp, TxConfig, (RTL_R32(tp, TxConfig) | BIT_25) & ~(BIT_19 | BIT_24));
1689
                         }
1690
 
1691
                         if (tp->mcfg == CFG_METHOD_21 || tp->mcfg == CFG_METHOD_22 ||
1692
                             tp->mcfg == CFG_METHOD_27 || tp->mcfg == CFG_METHOD_28 ||
1693
-                            tp->mcfg == CFG_METHOD_31 || tp->mcfg == CFG_METHOD_32) {
1694
+                            tp->mcfg == CFG_METHOD_31 || tp->mcfg == CFG_METHOD_32 ||
1695
+                            tp->mcfg == CFG_METHOD_33) {
1696
                                 /*half mode*/
1697
-                                if (!(RTL_R8(PHYstatus)&FullDup)) {
1698
+                                if (!(RTL_R8(tp, PHYstatus)&FullDup)) {
1699
                                         rtl8168_mdio_write(tp, 0x1F, 0x0000);
1700
                                         rtl8168_mdio_write(tp, MII_ADVERTISE, rtl8168_mdio_read(tp, MII_ADVERTISE)&~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM));
1701
                                 }
1702
                         }
1703
 
1704
-                        if ((tp->mcfg == CFG_METHOD_31 || tp->mcfg == CFG_METHOD_32) && (RTL_R8(PHYstatus) & _10bps)) {
1705
+                        if ((tp->mcfg == CFG_METHOD_31 || tp->mcfg == CFG_METHOD_32 ||
1706
+                             tp->mcfg == CFG_METHOD_33) && (RTL_R8(tp, PHYstatus) & _10bps)) {
1707
                                 u32 csi_tmp;
1708
 
1709
-                                csi_tmp = rtl8168_eri_read(ioaddr, 0x1D0, 1, ERIAR_ExGMAC);
1710
+                                csi_tmp = rtl8168_eri_read(tp, 0x1D0, 1, ERIAR_ExGMAC);
1711
                                 csi_tmp |= BIT_1;
1712
-                                rtl8168_eri_write(ioaddr, 0x1D0, 1, csi_tmp, ERIAR_ExGMAC);
1713
+                                rtl8168_eri_write(tp, 0x1D0, 1, csi_tmp, ERIAR_ExGMAC);
1714
                         }
1715
 
1716
                         rtl8168_hw_start(dev);
1717
@@ -3827,7 +3849,7 @@
1718
                 case CFG_METHOD_27:
1719
                 case CFG_METHOD_28:
1720
                         if (tp->issue_offset_99_event) {
1721
-                                if (!(RTL_R8(PHYstatus) & PowerSaveStatus)) {
1722
+                                if (!(RTL_R8(tp, PHYstatus) & PowerSaveStatus)) {
1723
                                         tp->issue_offset_99_event = FALSE;
1724
                                         rtl8168_issue_offset_99_event(tp);
1725
                                 }
1726
@@ -3876,7 +3898,8 @@
1727
         if (tp->mcfg == CFG_METHOD_25 || tp->mcfg == CFG_METHOD_26 ||
1728
             tp->mcfg == CFG_METHOD_27 || tp->mcfg == CFG_METHOD_28 ||
1729
             tp->mcfg == CFG_METHOD_29 || tp->mcfg == CFG_METHOD_30 ||
1730
-            tp->mcfg == CFG_METHOD_31 || tp->mcfg == CFG_METHOD_32) {
1731
+            tp->mcfg == CFG_METHOD_31 || tp->mcfg == CFG_METHOD_32 ||
1732
+            tp->mcfg == CFG_METHOD_33) {
1733
                 val = rtl8168_mdio_read_phy_ocp(tp, 0x0C41, 0x13);
1734
                 if (val != 0x0050) {
1735
                         rtl8168_set_phy_mcu_patch_request(tp);
1736
@@ -3896,7 +3919,8 @@
1737
         if (tp->mcfg == CFG_METHOD_25 || tp->mcfg == CFG_METHOD_26 ||
1738
             tp->mcfg == CFG_METHOD_27 || tp->mcfg == CFG_METHOD_28 ||
1739
             tp->mcfg == CFG_METHOD_29 || tp->mcfg == CFG_METHOD_30 ||
1740
-            tp->mcfg == CFG_METHOD_31 || tp->mcfg == CFG_METHOD_32) {
1741
+            tp->mcfg == CFG_METHOD_31 || tp->mcfg == CFG_METHOD_32 ||
1742
+            tp->mcfg == CFG_METHOD_33) {
1743
                 val = rtl8168_mdio_read_phy_ocp(tp, 0x0C41, 0x13);
1744
                 if (val != 0x0500) {
1745
                         rtl8168_set_phy_mcu_patch_request(tp);
1746
@@ -3911,12 +3935,11 @@
1747
 rtl8168_wait_ll_share_fifo_ready(struct net_device *dev)
1748
 {
1749
         struct rtl8168_private *tp = netdev_priv(dev);
1750
-        void __iomem *ioaddr = tp->mmio_addr;
1751
         int i;
1752
 
1753
         for (i = 0; i < 10; i++) {
1754
                 udelay(100);
1755
-                if (RTL_R16(0xD2) & BIT_9)
1756
+                if (RTL_R16(tp, 0xD2) & BIT_9)
1757
                         break;
1758
         }
1759
 }
1760
@@ -3924,7 +3947,6 @@
1761
 static void
1762
 rtl8168_disable_pci_offset_99(struct rtl8168_private *tp)
1763
 {
1764
-        void __iomem *ioaddr = tp->mmio_addr;
1765
         u32 csi_tmp;
1766
 
1767
         switch (tp->mcfg) {
1768
@@ -3940,9 +3962,10 @@
1769
         case CFG_METHOD_30:
1770
         case CFG_METHOD_31:
1771
         case CFG_METHOD_32:
1772
-                csi_tmp = rtl8168_eri_read(ioaddr, 0x3F2, 2, ERIAR_ExGMAC);
1773
+        case CFG_METHOD_33:
1774
+                csi_tmp = rtl8168_eri_read(tp, 0x3F2, 2, ERIAR_ExGMAC);
1775
                 csi_tmp &= ~(BIT_0 | BIT_1);
1776
-                rtl8168_eri_write(ioaddr, 0x3F2, 2, csi_tmp, ERIAR_ExGMAC);
1777
+                rtl8168_eri_write(tp, 0x3F2, 2, csi_tmp, ERIAR_ExGMAC);
1778
                 break;
1779
         }
1780
 
1781
@@ -3954,6 +3977,7 @@
1782
         case CFG_METHOD_30:
1783
         case CFG_METHOD_31:
1784
         case CFG_METHOD_32:
1785
+        case CFG_METHOD_33:
1786
                 rtl8168_csi_fun0_write_byte(tp, 0x99, 0x00);
1787
                 break;
1788
         }
1789
@@ -3962,7 +3986,6 @@
1790
 static void
1791
 rtl8168_enable_pci_offset_99(struct rtl8168_private *tp)
1792
 {
1793
-        void __iomem *ioaddr = tp->mmio_addr;
1794
         u32 csi_tmp;
1795
 
1796
         switch (tp->mcfg) {
1797
@@ -3973,6 +3996,7 @@
1798
         case CFG_METHOD_30:
1799
         case CFG_METHOD_31:
1800
         case CFG_METHOD_32:
1801
+        case CFG_METHOD_33:
1802
                 rtl8168_csi_fun0_write_byte(tp, 0x99, tp->org_pci_offset_99);
1803
                 break;
1804
         }
1805
@@ -3990,13 +4014,14 @@
1806
         case CFG_METHOD_30:
1807
         case CFG_METHOD_31:
1808
         case CFG_METHOD_32:
1809
-                csi_tmp = rtl8168_eri_read(ioaddr, 0x3F2, 2, ERIAR_ExGMAC);
1810
+        case CFG_METHOD_33:
1811
+                csi_tmp = rtl8168_eri_read(tp, 0x3F2, 2, ERIAR_ExGMAC);
1812
                 csi_tmp &= ~(BIT_0 | BIT_1);
1813
                 if (!(tp->org_pci_offset_99 & (BIT_5 | BIT_6)))
1814
                         csi_tmp |= BIT_1;
1815
                 if (!(tp->org_pci_offset_99 & BIT_2))
1816
                         csi_tmp |= BIT_0;
1817
-                rtl8168_eri_write(ioaddr, 0x3F2, 2, csi_tmp, ERIAR_ExGMAC);
1818
+                rtl8168_eri_write(tp, 0x3F2, 2, csi_tmp, ERIAR_ExGMAC);
1819
                 break;
1820
         }
1821
 }
1822
@@ -4004,15 +4029,14 @@
1823
 static void
1824
 rtl8168_init_pci_offset_99(struct rtl8168_private *tp)
1825
 {
1826
-        void __iomem *ioaddr = tp->mmio_addr;
1827
         u32 csi_tmp;
1828
 
1829
         switch (tp->mcfg) {
1830
         case CFG_METHOD_26:
1831
                 if (tp->org_pci_offset_99 & BIT_2) {
1832
-                        csi_tmp = rtl8168_eri_read(ioaddr, 0x5C2, 1, ERIAR_ExGMAC);
1833
+                        csi_tmp = rtl8168_eri_read(tp, 0x5C2, 1, ERIAR_ExGMAC);
1834
                         csi_tmp &= ~BIT_1;
1835
-                        rtl8168_eri_write(ioaddr, 0x5C2, 1, csi_tmp, ERIAR_ExGMAC);
1836
+                        rtl8168_eri_write(tp, 0x5C2, 1, csi_tmp, ERIAR_ExGMAC);
1837
                 }
1838
                 break;
1839
         }
1840
@@ -4030,13 +4054,14 @@
1841
         case CFG_METHOD_30:
1842
         case CFG_METHOD_31:
1843
         case CFG_METHOD_32:
1844
-                csi_tmp = rtl8168_eri_read(ioaddr, 0x3F2, 2, ERIAR_ExGMAC);
1845
+        case CFG_METHOD_33:
1846
+                csi_tmp = rtl8168_eri_read(tp, 0x3F2, 2, ERIAR_ExGMAC);
1847
                 csi_tmp &= ~( BIT_8 | BIT_9  | BIT_10 | BIT_11  | BIT_12  | BIT_13  | BIT_14 | BIT_15 );
1848
                 csi_tmp |= ( BIT_9 | BIT_10 | BIT_13  | BIT_14 | BIT_15 );
1849
-                rtl8168_eri_write(ioaddr, 0x3F2, 2, csi_tmp, ERIAR_ExGMAC);
1850
-                csi_tmp = rtl8168_eri_read(ioaddr, 0x3F5, 1, ERIAR_ExGMAC);
1851
+                rtl8168_eri_write(tp, 0x3F2, 2, csi_tmp, ERIAR_ExGMAC);
1852
+                csi_tmp = rtl8168_eri_read(tp, 0x3F5, 1, ERIAR_ExGMAC);
1853
                 csi_tmp |= BIT_6 | BIT_7;
1854
-                rtl8168_eri_write(ioaddr, 0x3F5, 1, csi_tmp, ERIAR_ExGMAC);
1855
+                rtl8168_eri_write(tp, 0x3F5, 1, csi_tmp, ERIAR_ExGMAC);
1856
                 rtl8168_mac_ocp_write(tp, 0xE02C, 0x1880);
1857
                 rtl8168_mac_ocp_write(tp, 0xE02E, 0x4880);
1858
                 break;
1859
@@ -4044,22 +4069,23 @@
1860
 
1861
         switch (tp->mcfg) {
1862
         case CFG_METHOD_26:
1863
-                rtl8168_eri_write(ioaddr, 0x5C0, 1, 0xFA, ERIAR_ExGMAC);
1864
+                rtl8168_eri_write(tp, 0x5C0, 1, 0xFA, ERIAR_ExGMAC);
1865
                 break;
1866
         }
1867
 
1868
         switch (tp->mcfg) {
1869
         case CFG_METHOD_26:
1870
                 if (tp->org_pci_offset_99 & BIT_2) {
1871
-                        csi_tmp = rtl8168_eri_read(ioaddr, 0x5C8, 1, ERIAR_ExGMAC);
1872
+                        csi_tmp = rtl8168_eri_read(tp, 0x5C8, 1, ERIAR_ExGMAC);
1873
                         csi_tmp |= BIT_0;
1874
-                        rtl8168_eri_write(ioaddr, 0x5C8, 1, csi_tmp, ERIAR_ExGMAC);
1875
+                        rtl8168_eri_write(tp, 0x5C8, 1, csi_tmp, ERIAR_ExGMAC);
1876
                 }
1877
                 break;
1878
         case CFG_METHOD_29:
1879
         case CFG_METHOD_30:
1880
         case CFG_METHOD_31:
1881
         case CFG_METHOD_32:
1882
+        case CFG_METHOD_33:
1883
                 if (tp->org_pci_offset_99 & BIT_2)
1884
                         rtl8168_mac_ocp_write(tp, 0xE0A2,  rtl8168_mac_ocp_read(tp, 0xE0A2) | BIT_0);
1885
                 break;
1886
@@ -4067,12 +4093,12 @@
1887
 
1888
         switch (tp->mcfg) {
1889
         case CFG_METHOD_23:
1890
-                rtl8168_eri_write(ioaddr, 0x2E8, 2, 0x883C, ERIAR_ExGMAC);
1891
-                rtl8168_eri_write(ioaddr, 0x2EA, 2, 0x8C12, ERIAR_ExGMAC);
1892
-                rtl8168_eri_write(ioaddr, 0x2EC, 2, 0x9003, ERIAR_ExGMAC);
1893
-                rtl8168_eri_write(ioaddr, 0x2E2, 2, 0x883C, ERIAR_ExGMAC);
1894
-                rtl8168_eri_write(ioaddr, 0x2E4, 2, 0x8C12, ERIAR_ExGMAC);
1895
-                rtl8168_eri_write(ioaddr, 0x2E6, 2, 0x9003, ERIAR_ExGMAC);
1896
+                rtl8168_eri_write(tp, 0x2E8, 2, 0x883C, ERIAR_ExGMAC);
1897
+                rtl8168_eri_write(tp, 0x2EA, 2, 0x8C12, ERIAR_ExGMAC);
1898
+                rtl8168_eri_write(tp, 0x2EC, 2, 0x9003, ERIAR_ExGMAC);
1899
+                rtl8168_eri_write(tp, 0x2E2, 2, 0x883C, ERIAR_ExGMAC);
1900
+                rtl8168_eri_write(tp, 0x2E4, 2, 0x8C12, ERIAR_ExGMAC);
1901
+                rtl8168_eri_write(tp, 0x2E6, 2, 0x9003, ERIAR_ExGMAC);
1902
                 break;
1903
         case CFG_METHOD_21:
1904
         case CFG_METHOD_22:
1905
@@ -4085,12 +4111,13 @@
1906
         case CFG_METHOD_30:
1907
         case CFG_METHOD_31:
1908
         case CFG_METHOD_32:
1909
-                rtl8168_eri_write(ioaddr, 0x2E8, 2, 0x9003, ERIAR_ExGMAC);
1910
-                rtl8168_eri_write(ioaddr, 0x2EA, 2, 0x9003, ERIAR_ExGMAC);
1911
-                rtl8168_eri_write(ioaddr, 0x2EC, 2, 0x9003, ERIAR_ExGMAC);
1912
-                rtl8168_eri_write(ioaddr, 0x2E2, 2, 0x883C, ERIAR_ExGMAC);
1913
-                rtl8168_eri_write(ioaddr, 0x2E4, 2, 0x8C12, ERIAR_ExGMAC);
1914
-                rtl8168_eri_write(ioaddr, 0x2E6, 2, 0x9003, ERIAR_ExGMAC);
1915
+        case CFG_METHOD_33:
1916
+                rtl8168_eri_write(tp, 0x2E8, 2, 0x9003, ERIAR_ExGMAC);
1917
+                rtl8168_eri_write(tp, 0x2EA, 2, 0x9003, ERIAR_ExGMAC);
1918
+                rtl8168_eri_write(tp, 0x2EC, 2, 0x9003, ERIAR_ExGMAC);
1919
+                rtl8168_eri_write(tp, 0x2E2, 2, 0x883C, ERIAR_ExGMAC);
1920
+                rtl8168_eri_write(tp, 0x2E4, 2, 0x8C12, ERIAR_ExGMAC);
1921
+                rtl8168_eri_write(tp, 0x2E6, 2, 0x9003, ERIAR_ExGMAC);
1922
                 break;
1923
         }
1924
 
1925
@@ -4102,9 +4129,9 @@
1926
         case CFG_METHOD_26:
1927
         case CFG_METHOD_27:
1928
         case CFG_METHOD_28:
1929
-                csi_tmp = rtl8168_eri_read(ioaddr, 0x3FA, 2, ERIAR_ExGMAC);
1930
+                csi_tmp = rtl8168_eri_read(tp, 0x3FA, 2, ERIAR_ExGMAC);
1931
                 csi_tmp |= BIT_14;
1932
-                rtl8168_eri_write(ioaddr, 0x3FA, 2, csi_tmp, ERIAR_ExGMAC);
1933
+                rtl8168_eri_write(tp, 0x3FA, 2, csi_tmp, ERIAR_ExGMAC);
1934
                 break;
1935
         }
1936
 
1937
@@ -4113,7 +4140,7 @@
1938
         case CFG_METHOD_29:
1939
         case CFG_METHOD_30:
1940
                 if (tp->org_pci_offset_99 & BIT_2)
1941
-                        RTL_W8(0xB6, RTL_R8(0xB6) | BIT_0);
1942
+                        RTL_W8(tp, 0xB6, RTL_R8(tp, 0xB6) | BIT_0);
1943
                 break;
1944
         }
1945
 
1946
@@ -4123,7 +4150,6 @@
1947
 static void
1948
 rtl8168_disable_pci_offset_180(struct rtl8168_private *tp)
1949
 {
1950
-        void __iomem *ioaddr = tp->mmio_addr;
1951
         u32 csi_tmp;
1952
 
1953
         switch (tp->mcfg) {
1954
@@ -4136,15 +4162,16 @@
1955
         case CFG_METHOD_30:
1956
         case CFG_METHOD_31:
1957
         case CFG_METHOD_32:
1958
-                csi_tmp = rtl8168_eri_read(ioaddr, 0x1E2, 1, ERIAR_ExGMAC);
1959
+        case CFG_METHOD_33:
1960
+                csi_tmp = rtl8168_eri_read(tp, 0x1E2, 1, ERIAR_ExGMAC);
1961
                 csi_tmp &= ~BIT_2;
1962
-                rtl8168_eri_write(ioaddr, 0x1E2, 1, csi_tmp, ERIAR_ExGMAC);
1963
+                rtl8168_eri_write(tp, 0x1E2, 1, csi_tmp, ERIAR_ExGMAC);
1964
                 break;
1965
         }
1966
 
1967
         switch (tp->mcfg) {
1968
         case CFG_METHOD_26:
1969
-                rtl8168_eri_write(ioaddr, 0x1E9, 1, 0x0A, ERIAR_ExGMAC);
1970
+                rtl8168_eri_write(tp, 0x1E9, 1, 0x0A, ERIAR_ExGMAC);
1971
                 break;
1972
         }
1973
 }
1974
@@ -4152,31 +4179,31 @@
1975
 static void
1976
 rtl8168_enable_pci_offset_180(struct rtl8168_private *tp)
1977
 {
1978
-        void __iomem *ioaddr = tp->mmio_addr;
1979
         u32 csi_tmp;
1980
 
1981
         switch (tp->mcfg) {
1982
         case CFG_METHOD_25:
1983
         case CFG_METHOD_28:
1984
-                csi_tmp = rtl8168_eri_read(ioaddr, 0x1E8, 4, ERIAR_ExGMAC);
1985
+                csi_tmp = rtl8168_eri_read(tp, 0x1E8, 4, ERIAR_ExGMAC);
1986
                 csi_tmp &= ~(0x0000FF00);
1987
                 csi_tmp |= (0x00006400);
1988
-                rtl8168_eri_write(ioaddr, 0x1E8, 4, csi_tmp, ERIAR_ExGMAC);
1989
+                rtl8168_eri_write(tp, 0x1E8, 4, csi_tmp, ERIAR_ExGMAC);
1990
 
1991
-                csi_tmp = rtl8168_eri_read(ioaddr, 0x1E4, 4, ERIAR_ExGMAC);
1992
+                csi_tmp = rtl8168_eri_read(tp, 0x1E4, 4, ERIAR_ExGMAC);
1993
                 csi_tmp &= ~(0x0000FF00);
1994
-                rtl8168_eri_write(ioaddr, 0x1E4, 4, csi_tmp, ERIAR_ExGMAC);
1995
+                rtl8168_eri_write(tp, 0x1E4, 4, csi_tmp, ERIAR_ExGMAC);
1996
                 break;
1997
         case CFG_METHOD_31:
1998
         case CFG_METHOD_32:
1999
-                csi_tmp = rtl8168_eri_read(ioaddr, 0x1E8, 4, ERIAR_ExGMAC);
2000
+        case CFG_METHOD_33:
2001
+                csi_tmp = rtl8168_eri_read(tp, 0x1E8, 4, ERIAR_ExGMAC);
2002
                 csi_tmp &= ~(0x0000FFF0);
2003
                 csi_tmp |= (0x00000640);
2004
-                rtl8168_eri_write(ioaddr, 0x1E8, 4, csi_tmp, ERIAR_ExGMAC);
2005
+                rtl8168_eri_write(tp, 0x1E8, 4, csi_tmp, ERIAR_ExGMAC);
2006
 
2007
-                csi_tmp = rtl8168_eri_read(ioaddr, 0x1E4, 4, ERIAR_ExGMAC);
2008
+                csi_tmp = rtl8168_eri_read(tp, 0x1E4, 4, ERIAR_ExGMAC);
2009
                 csi_tmp &= ~(0x0000FF00);
2010
-                rtl8168_eri_write(ioaddr, 0x1E4, 4, csi_tmp, ERIAR_ExGMAC);
2011
+                rtl8168_eri_write(tp, 0x1E4, 4, csi_tmp, ERIAR_ExGMAC);
2012
                 break;
2013
         }
2014
 
2015
@@ -4188,15 +4215,15 @@
2016
         case CFG_METHOD_28:
2017
         case CFG_METHOD_29:
2018
         case CFG_METHOD_30:
2019
-                csi_tmp = rtl8168_eri_read(ioaddr, 0x1E2, 1, ERIAR_ExGMAC);
2020
+                csi_tmp = rtl8168_eri_read(tp, 0x1E2, 1, ERIAR_ExGMAC);
2021
                 csi_tmp |= BIT_2;
2022
-                rtl8168_eri_write(ioaddr, 0x1E2, 1, csi_tmp, ERIAR_ExGMAC);
2023
+                rtl8168_eri_write(tp, 0x1E2, 1, csi_tmp, ERIAR_ExGMAC);
2024
                 break;
2025
         }
2026
 
2027
         switch (tp->mcfg) {
2028
         case CFG_METHOD_26:
2029
-                rtl8168_eri_write(ioaddr, 0x1E9, 1, 0x64, ERIAR_ExGMAC);
2030
+                rtl8168_eri_write(tp, 0x1E9, 1, 0x64, ERIAR_ExGMAC);
2031
                 break;
2032
         }
2033
 
2034
@@ -4229,6 +4256,7 @@
2035
         case CFG_METHOD_30:
2036
         case CFG_METHOD_31:
2037
         case CFG_METHOD_32:
2038
+        case CFG_METHOD_33:
2039
                 rtl8168_issue_offset_99_event(tp);
2040
                 break;
2041
         }
2042
@@ -4246,6 +4274,7 @@
2043
         case CFG_METHOD_30:
2044
         case CFG_METHOD_31:
2045
         case CFG_METHOD_32:
2046
+        case CFG_METHOD_33:
2047
                 rtl8168_disable_pci_offset_99(tp);
2048
                 break;
2049
         }
2050
@@ -4259,6 +4288,7 @@
2051
         case CFG_METHOD_30:
2052
         case CFG_METHOD_31:
2053
         case CFG_METHOD_32:
2054
+        case CFG_METHOD_33:
2055
                 rtl8168_disable_pci_offset_180(tp);
2056
                 break;
2057
         }
2058
@@ -4267,26 +4297,21 @@
2059
 static void
2060
 rtl8168_enable_cfg9346_write(struct rtl8168_private *tp)
2061
 {
2062
-        void __iomem *ioaddr = tp->mmio_addr;
2063
-
2064
-        RTL_W8(Cfg9346, RTL_R8(Cfg9346) | Cfg9346_Unlock);
2065
+        RTL_W8(tp, Cfg9346, RTL_R8(tp, Cfg9346) | Cfg9346_Unlock);
2066
 }
2067
 
2068
 static void
2069
 rtl8168_disable_cfg9346_write(struct rtl8168_private *tp)
2070
 {
2071
-        void __iomem *ioaddr = tp->mmio_addr;
2072
-
2073
-        RTL_W8(Cfg9346, RTL_R8(Cfg9346) & ~Cfg9346_Unlock);
2074
+        RTL_W8(tp, Cfg9346, RTL_R8(tp, Cfg9346) & ~Cfg9346_Unlock);
2075
 }
2076
 
2077
 static void
2078
 rtl8168_hw_d3_para(struct net_device *dev)
2079
 {
2080
         struct rtl8168_private *tp = netdev_priv(dev);
2081
-        void __iomem *ioaddr = tp->mmio_addr;
2082
 
2083
-        RTL_W16(RxMaxSize, RX_BUF_SIZE);
2084
+        RTL_W16(tp, RxMaxSize, RX_BUF_SIZE);
2085
 
2086
         switch (tp->mcfg) {
2087
         case CFG_METHOD_14:
2088
@@ -4308,10 +4333,11 @@
2089
         case CFG_METHOD_30:
2090
         case CFG_METHOD_31:
2091
         case CFG_METHOD_32:
2092
-                RTL_W8(0xF1, RTL_R8(0xF1) & ~BIT_7);
2093
+        case CFG_METHOD_33:
2094
+                RTL_W8(tp, 0xF1, RTL_R8(tp, 0xF1) & ~BIT_7);
2095
                 rtl8168_enable_cfg9346_write(tp);
2096
-                RTL_W8(Config2, RTL_R8(Config2) & ~BIT_7);
2097
-                RTL_W8(Config5, RTL_R8(Config5) & ~BIT_0);
2098
+                RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~BIT_7);
2099
+                RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~BIT_0);
2100
                 rtl8168_disable_cfg9346_write(tp);
2101
                 break;
2102
         }
2103
@@ -4321,19 +4347,20 @@
2104
 #endif
2105
 
2106
         if (tp->mcfg == CFG_METHOD_18 || tp->mcfg == CFG_METHOD_19 || tp->mcfg == CFG_METHOD_20) {
2107
-                rtl8168_eri_write(ioaddr, 0x1bc, 4, 0x0000001f, ERIAR_ExGMAC);
2108
-                rtl8168_eri_write(ioaddr, 0x1dc, 4, 0x0000002d, ERIAR_ExGMAC);
2109
+                rtl8168_eri_write(tp, 0x1bc, 4, 0x0000001f, ERIAR_ExGMAC);
2110
+                rtl8168_eri_write(tp, 0x1dc, 4, 0x0000002d, ERIAR_ExGMAC);
2111
         } else if (tp->mcfg == CFG_METHOD_16) {
2112
-                rtl8168_eri_write(ioaddr, 0x1bc, 4, 0x0000001f, ERIAR_ExGMAC);
2113
-                rtl8168_eri_write(ioaddr, 0x1dc, 4, 0x0000003f, ERIAR_ExGMAC);
2114
+                rtl8168_eri_write(tp, 0x1bc, 4, 0x0000001f, ERIAR_ExGMAC);
2115
+                rtl8168_eri_write(tp, 0x1dc, 4, 0x0000003f, ERIAR_ExGMAC);
2116
         }
2117
 
2118
         if (tp->mcfg == CFG_METHOD_21 || tp->mcfg == CFG_METHOD_22 ||
2119
             tp->mcfg == CFG_METHOD_23 || tp->mcfg == CFG_METHOD_24 ||
2120
             tp->mcfg == CFG_METHOD_25 || tp->mcfg == CFG_METHOD_26 ||
2121
             tp->mcfg == CFG_METHOD_27 || tp->mcfg == CFG_METHOD_28 ||
2122
-            tp->mcfg == CFG_METHOD_31 || tp->mcfg == CFG_METHOD_32) {
2123
-                rtl8168_eri_write(ioaddr, 0x2F8, 2, 0x0064, ERIAR_ExGMAC);
2124
+            tp->mcfg == CFG_METHOD_31 || tp->mcfg == CFG_METHOD_32 ||
2125
+            tp->mcfg == CFG_METHOD_33) {
2126
+                rtl8168_eri_write(tp, 0x2F8, 2, 0x0064, ERIAR_ExGMAC);
2127
         }
2128
 
2129
         if (tp->bios_setting & BIT_28) {
2130
@@ -4360,17 +4387,14 @@
2131
                 }
2132
         }
2133
 
2134
-        if (tp->mcfg == CFG_METHOD_31 || tp->mcfg == CFG_METHOD_32) {
2135
-                rtl8168_set_dash_other_fun_dev_state_change(tp, 3, 0xFD);
2136
-        }
2137
-
2138
         rtl8168_set_pci_99_180_exit_driver_para(dev);
2139
 
2140
         /*disable ocp phy power saving*/
2141
         if (tp->mcfg == CFG_METHOD_25 || tp->mcfg == CFG_METHOD_26 ||
2142
             tp->mcfg == CFG_METHOD_27 || tp->mcfg == CFG_METHOD_28 ||
2143
             tp->mcfg == CFG_METHOD_29 || tp->mcfg == CFG_METHOD_30 ||
2144
-            tp->mcfg == CFG_METHOD_31 || tp->mcfg == CFG_METHOD_32)
2145
+            tp->mcfg == CFG_METHOD_31 || tp->mcfg == CFG_METHOD_32 ||
2146
+            tp->mcfg == CFG_METHOD_33)
2147
                 if (!tp->dash_printer_enabled)
2148
                         rtl8168_disable_ocp_phy_power_saving(dev);
2149
 
2150
@@ -4381,19 +4405,18 @@
2151
 rtl8168_enable_magic_packet(struct net_device *dev)
2152
 {
2153
         struct rtl8168_private *tp = netdev_priv(dev);
2154
-        void __iomem *ioaddr = tp->mmio_addr;
2155
         u32 csi_tmp;
2156
 
2157
         switch (tp->HwSuppMagicPktVer) {
2158
         case WAKEUP_MAGIC_PACKET_V1:
2159
                 rtl8168_enable_cfg9346_write(tp);
2160
-                RTL_W8(Config3, RTL_R8(Config3) | MagicPacket);
2161
+                RTL_W8(tp, Config3, RTL_R8(tp, Config3) | MagicPacket);
2162
                 rtl8168_disable_cfg9346_write(tp);
2163
                 break;
2164
         case WAKEUP_MAGIC_PACKET_V2:
2165
-                csi_tmp = rtl8168_eri_read(ioaddr, 0xDE, 1, ERIAR_ExGMAC);
2166
+                csi_tmp = rtl8168_eri_read(tp, 0xDE, 1, ERIAR_ExGMAC);
2167
                 csi_tmp |= BIT_0;
2168
-                rtl8168_eri_write(ioaddr, 0xDE, 1, csi_tmp, ERIAR_ExGMAC);
2169
+                rtl8168_eri_write(tp, 0xDE, 1, csi_tmp, ERIAR_ExGMAC);
2170
                 break;
2171
         }
2172
 }
2173
@@ -4401,19 +4424,18 @@
2174
 rtl8168_disable_magic_packet(struct net_device *dev)
2175
 {
2176
         struct rtl8168_private *tp = netdev_priv(dev);
2177
-        void __iomem *ioaddr = tp->mmio_addr;
2178
         u32 csi_tmp;
2179
 
2180
         switch (tp->HwSuppMagicPktVer) {
2181
         case WAKEUP_MAGIC_PACKET_V1:
2182
                 rtl8168_enable_cfg9346_write(tp);
2183
-                RTL_W8(Config3, RTL_R8(Config3) & ~MagicPacket);
2184
+                RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~MagicPacket);
2185
                 rtl8168_disable_cfg9346_write(tp);
2186
                 break;
2187
         case WAKEUP_MAGIC_PACKET_V2:
2188
-                csi_tmp = rtl8168_eri_read(ioaddr, 0xDE, 1, ERIAR_ExGMAC);
2189
+                csi_tmp = rtl8168_eri_read(tp, 0xDE, 1, ERIAR_ExGMAC);
2190
                 csi_tmp &= ~BIT_0;
2191
-                rtl8168_eri_write(ioaddr, 0xDE, 1, csi_tmp, ERIAR_ExGMAC);
2192
+                rtl8168_eri_write(tp, 0xDE, 1, csi_tmp, ERIAR_ExGMAC);
2193
                 break;
2194
         }
2195
 }
2196
@@ -4424,7 +4446,6 @@
2197
 rtl8168_get_hw_wol(struct net_device *dev)
2198
 {
2199
         struct rtl8168_private *tp = netdev_priv(dev);
2200
-        void __iomem *ioaddr = tp->mmio_addr;
2201
         u8 options;
2202
         u32 csi_tmp;
2203
         unsigned long flags;
2204
@@ -4433,17 +4454,17 @@
2205
         spin_lock_irqsave(&tp->lock, flags);
2206
 
2207
         tp->wol_opts = 0;
2208
-        options = RTL_R8(Config1);
2209
+        options = RTL_R8(tp, Config1);
2210
         if (!(options & PMEnable))
2211
                 goto out_unlock;
2212
 
2213
-        options = RTL_R8(Config3);
2214
+        options = RTL_R8(tp, Config3);
2215
         if (options & LinkUp)
2216
                 tp->wol_opts |= WAKE_PHY;
2217
 
2218
         switch (tp->HwSuppMagicPktVer) {
2219
         case WAKEUP_MAGIC_PACKET_V2:
2220
-                csi_tmp = rtl8168_eri_read(ioaddr, 0xDE, 1, ERIAR_ExGMAC);
2221
+                csi_tmp = rtl8168_eri_read(tp, 0xDE, 1, ERIAR_ExGMAC);
2222
                 if (csi_tmp & BIT_0)
2223
                         tp->wol_opts |= WAKE_MAGIC;
2224
                 break;
2225
@@ -4453,7 +4474,7 @@
2226
                 break;
2227
         }
2228
 
2229
-        options = RTL_R8(Config5);
2230
+        options = RTL_R8(tp, Config5);
2231
         if (options & UWF)
2232
                 tp->wol_opts |= WAKE_UCAST;
2233
         if (options & BWF)
2234
@@ -4471,7 +4492,6 @@
2235
 rtl8168_set_hw_wol(struct net_device *dev, u32 wolopts)
2236
 {
2237
         struct rtl8168_private *tp = netdev_priv(dev);
2238
-        void __iomem *ioaddr = tp->mmio_addr;
2239
         int i,tmp;
2240
         static struct {
2241
                 u32 opt;
2242
@@ -4503,10 +4523,10 @@
2243
         rtl8168_enable_cfg9346_write(tp);
2244
 
2245
         for (i = 0; i < tmp; i++) {
2246
-                u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
2247
+                u8 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;
2248
                 if (wolopts & cfg[i].opt)
2249
                         options |= cfg[i].mask;
2250
-                RTL_W8(cfg[i].reg, options);
2251
+                RTL_W8(tp, cfg[i].reg, options);
2252
         }
2253
 
2254
         rtl8168_disable_cfg9346_write(tp);
2255
@@ -4555,7 +4575,6 @@
2256
 rtl8168_powerdown_pll(struct net_device *dev)
2257
 {
2258
         struct rtl8168_private *tp = netdev_priv(dev);
2259
-        void __iomem *ioaddr = tp->mmio_addr;
2260
 
2261
 #ifdef ENABLE_FIBER_SUPPORT
2262
         if (HW_FIBER_MODE_ENABLED(tp))
2263
@@ -4575,9 +4594,10 @@
2264
                     tp->mcfg == CFG_METHOD_26 || tp->mcfg == CFG_METHOD_23 ||
2265
                     tp->mcfg == CFG_METHOD_27 || tp->mcfg == CFG_METHOD_28 ||
2266
                     tp->mcfg == CFG_METHOD_29 || tp->mcfg == CFG_METHOD_30 ||
2267
-                    tp->mcfg == CFG_METHOD_31 || tp->mcfg == CFG_METHOD_32) {
2268
+                    tp->mcfg == CFG_METHOD_31 || tp->mcfg == CFG_METHOD_32 ||
2269
+                    tp->mcfg == CFG_METHOD_33) {
2270
                         rtl8168_enable_cfg9346_write(tp);
2271
-                        RTL_W8(Config2, RTL_R8(Config2) | PMSTS_En);
2272
+                        RTL_W8(tp, Config2, RTL_R8(tp, Config2) | PMSTS_En);
2273
                         rtl8168_disable_cfg9346_write(tp);
2274
                 }
2275
 
2276
@@ -4603,7 +4623,7 @@
2277
                 if (tp->DASH)
2278
                         auto_nego |= (ADVERTISE_100FULL | ADVERTISE_100HALF | ADVERTISE_10HALF | ADVERTISE_10FULL);
2279
 
2280
-                if (((tp->mcfg == CFG_METHOD_7) || (tp->mcfg == CFG_METHOD_8)) && (RTL_R16(CPlusCmd) & ASF))
2281
+                if (((tp->mcfg == CFG_METHOD_7) || (tp->mcfg == CFG_METHOD_8)) && (RTL_R16(tp, CPlusCmd) & ASF))
2282
                         auto_nego |= (ADVERTISE_100FULL | ADVERTISE_100HALF | ADVERTISE_10HALF | ADVERTISE_10FULL);
2283
 
2284
                 giga_ctrl = rtl8168_mdio_read(tp, MII_CTRL1000) & ~(ADVERTISE_1000HALF | ADVERTISE_1000FULL);
2285
@@ -4611,7 +4631,7 @@
2286
                 rtl8168_mdio_write(tp, MII_CTRL1000, giga_ctrl);
2287
                 rtl8168_phy_restart_nway(dev);
2288
 
2289
-                RTL_W32(RxConfig, RTL_R32(RxConfig) | AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
2290
+                RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) | AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
2291
 
2292
                 return;
2293
         }
2294
@@ -4619,7 +4639,7 @@
2295
         if (tp->DASH)
2296
                 return;
2297
 
2298
-        if (((tp->mcfg == CFG_METHOD_7) || (tp->mcfg == CFG_METHOD_8)) && (RTL_R16(CPlusCmd) & ASF))
2299
+        if (((tp->mcfg == CFG_METHOD_7) || (tp->mcfg == CFG_METHOD_8)) && (RTL_R16(tp, CPlusCmd) & ASF))
2300
                 return;
2301
 
2302
         rtl8168_phy_power_down(dev);
2303
@@ -4646,17 +4666,18 @@
2304
         case CFG_METHOD_30:
2305
         case CFG_METHOD_31:
2306
         case CFG_METHOD_32:
2307
-                RTL_W8(PMCH, RTL_R8(PMCH) & ~BIT_7);
2308
+        case CFG_METHOD_33:
2309
+                RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~BIT_7);
2310
                 break;
2311
         }
2312
 
2313
         switch (tp->mcfg) {
2314
         case CFG_METHOD_14 ... CFG_METHOD_15:
2315
-                RTL_W8(0xD0, RTL_R8(0xD0) & ~BIT_6);
2316
+                RTL_W8(tp, 0xD0, RTL_R8(tp, 0xD0) & ~BIT_6);
2317
                 break;
2318
-        case CFG_METHOD_16 ... CFG_METHOD_32:
2319
-                RTL_W8(0xD0, RTL_R8(0xD0) & ~BIT_6);
2320
-                RTL_W8(0xF2, RTL_R8(0xF2) & ~BIT_6);
2321
+        case CFG_METHOD_16 ... CFG_METHOD_33:
2322
+                RTL_W8(tp, 0xD0, RTL_R8(tp, 0xD0) & ~BIT_6);
2323
+                RTL_W8(tp, 0xF2, RTL_R8(tp, 0xF2) & ~BIT_6);
2324
                 break;
2325
         }
2326
 }
2327
@@ -4664,8 +4685,6 @@
2328
 static void rtl8168_powerup_pll(struct net_device *dev)
2329
 {
2330
         struct rtl8168_private *tp = netdev_priv(dev);
2331
-        void __iomem *ioaddr = tp->mmio_addr;
2332
-
2333
 
2334
         switch (tp->mcfg) {
2335
         case CFG_METHOD_9:
2336
@@ -4689,7 +4708,8 @@
2337
         case CFG_METHOD_30:
2338
         case CFG_METHOD_31:
2339
         case CFG_METHOD_32:
2340
-                RTL_W8(PMCH, RTL_R8(PMCH) | BIT_7 | BIT_6);
2341
+        case CFG_METHOD_33:
2342
+                RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | BIT_7 | BIT_6);
2343
                 break;
2344
         }
2345
 
2346
@@ -4702,7 +4722,6 @@
2347
                 struct ethtool_wolinfo *wol)
2348
 {
2349
         struct rtl8168_private *tp = netdev_priv(dev);
2350
-        void __iomem *ioaddr = tp->mmio_addr;
2351
         u8 options;
2352
         unsigned long flags;
2353
 
2354
@@ -4717,7 +4736,7 @@
2355
 
2356
         spin_lock_irqsave(&tp->lock, flags);
2357
 
2358
-        options = RTL_R8(Config1);
2359
+        options = RTL_R8(tp, Config1);
2360
         if (!(options & PMEnable))
2361
                 goto out_unlock;
2362
 
2363
@@ -4783,11 +4802,13 @@
2364
         int rc = -EINVAL;
2365
 
2366
         if (tp->mcfg == CFG_METHOD_29 || tp->mcfg == CFG_METHOD_30 ||
2367
-            tp->mcfg == CFG_METHOD_31 || tp->mcfg == CFG_METHOD_32) {
2368
+            tp->mcfg == CFG_METHOD_31 || tp->mcfg == CFG_METHOD_32 ||
2369
+            tp->mcfg == CFG_METHOD_33) {
2370
                 //Disable Giga Lite
2371
                 rtl8168_mdio_write(tp, 0x1F, 0x0A42);
2372
                 rtl8168_clear_eth_phy_bit(tp, 0x14, BIT_9);
2373
-                if (tp->mcfg == CFG_METHOD_31 || tp->mcfg == CFG_METHOD_32)
2374
+                if (tp->mcfg == CFG_METHOD_31 || tp->mcfg == CFG_METHOD_32 ||
2375
+                    tp->mcfg == CFG_METHOD_33)
2376
                         rtl8168_clear_eth_phy_bit(tp, 0x14, BIT_7);
2377
                 rtl8168_mdio_write(tp, 0x1F, 0x0A40);
2378
                 rtl8168_mdio_write(tp, 0x1F, 0x0000);
2379
@@ -4987,7 +5008,6 @@
2380
                     u32 data)
2381
 {
2382
         struct rtl8168_private *tp = netdev_priv(dev);
2383
-        void __iomem *ioaddr = tp->mmio_addr;
2384
         unsigned long flags;
2385
 
2386
         if (tp->mcfg == CFG_METHOD_DEFAULT)
2387
@@ -5000,7 +5020,7 @@
2388
         else
2389
                 tp->cp_cmd &= ~RxChkSum;
2390
 
2391
-        RTL_W16(CPlusCmd, tp->cp_cmd);
2392
+        RTL_W16(tp, CPlusCmd, tp->cp_cmd);
2393
 
2394
         spin_unlock_irqrestore(&tp->lock, flags);
2395
 
2396
@@ -5038,7 +5058,6 @@
2397
                          struct vlan_group *grp)
2398
 {
2399
         struct rtl8168_private *tp = netdev_priv(dev);
2400
-        void __iomem *ioaddr = tp->mmio_addr;
2401
         unsigned long flags;
2402
 
2403
         spin_lock_irqsave(&tp->lock, flags);
2404
@@ -5047,8 +5066,8 @@
2405
                 tp->cp_cmd |= RxVlan;
2406
         else
2407
                 tp->cp_cmd &= ~RxVlan;
2408
-        RTL_W16(CPlusCmd, tp->cp_cmd);
2409
-        RTL_R16(CPlusCmd);
2410
+        RTL_W16(tp, CPlusCmd, tp->cp_cmd);
2411
+        RTL_R16(tp, CPlusCmd);
2412
         spin_unlock_irqrestore(&tp->lock, flags);
2413
 }
2414
 
2415
@@ -5142,16 +5161,15 @@
2416
                                    netdev_features_t features)
2417
 {
2418
         struct rtl8168_private *tp = netdev_priv(dev);
2419
-        void __iomem *ioaddr = tp->mmio_addr;
2420
         u32 rx_config;
2421
 
2422
-        rx_config = RTL_R32(RxConfig);
2423
+        rx_config = RTL_R32(tp, RxConfig);
2424
         if (features & NETIF_F_RXALL)
2425
                 rx_config |= (AcceptErr | AcceptRunt);
2426
         else
2427
                 rx_config &= ~(AcceptErr | AcceptRunt);
2428
 
2429
-        RTL_W32(RxConfig, rx_config);
2430
+        RTL_W32(tp, RxConfig, rx_config);
2431
 
2432
         if (features & NETIF_F_RXCSUM)
2433
                 tp->cp_cmd |= RxChkSum;
2434
@@ -5163,8 +5181,8 @@
2435
         else
2436
                 tp->cp_cmd &= ~RxVlan;
2437
 
2438
-        RTL_W16(CPlusCmd, tp->cp_cmd);
2439
-        RTL_R16(CPlusCmd);
2440
+        RTL_W16(tp, CPlusCmd, tp->cp_cmd);
2441
+        RTL_R16(tp, CPlusCmd);
2442
 
2443
         return 0;
2444
 }
2445
@@ -5196,7 +5214,6 @@
2446
                              )
2447
 {
2448
         struct rtl8168_private *tp = netdev_priv(dev);
2449
-        void __iomem *ioaddr = tp->mmio_addr;
2450
         u8 status;
2451
         u8 autoneg, duplex;
2452
         u32 speed = 0;
2453
@@ -5252,7 +5269,7 @@
2454
                 lp_advertising = 0;
2455
         }
2456
 
2457
-        status = RTL_R8(PHYstatus);
2458
+        status = RTL_R8(tp, PHYstatus);
2459
 
2460
         if (status & LinkStatus) {
2461
                 /*link on*/
2462
@@ -5345,7 +5362,7 @@
2463
         data = (u8*)p + 256 * 2;
2464
 
2465
         for (i = 0; i < R8168_EPHY_REGS_SIZE/2; i++) {
2466
-                *(u16*)data = rtl8168_ephy_read(ioaddr, i);
2467
+                *(u16*)data = rtl8168_ephy_read(tp, i);
2468
                 data += 2;
2469
         }
2470
         data = (u8*)p + 256 * 3;
2471
@@ -5358,7 +5375,7 @@
2472
                 break;
2473
         default:
2474
                 for (i = 0; i < R8168_ERI_REGS_SIZE; i+=4) {
2475
-                        *(u32*)data = rtl8168_eri_read(ioaddr, i , 4, ERIAR_ExGMAC);
2476
+                        *(u32*)data = rtl8168_eri_read(tp, i , 4, ERIAR_ExGMAC);
2477
                         data += 4;
2478
                 }
2479
                 break;
2480
@@ -5426,7 +5443,6 @@
2481
                           u64 *data)
2482
 {
2483
         struct rtl8168_private *tp = netdev_priv(dev);
2484
-        void __iomem *ioaddr = tp->mmio_addr;
2485
         struct rtl8168_counters *counters;
2486
         dma_addr_t paddr;
2487
         u32 cmd;
2488
@@ -5441,13 +5457,13 @@
2489
                 return;
2490
 
2491
         spin_lock_irqsave(&tp->lock, flags);
2492
-        RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
2493
+        RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32);
2494
         cmd = (u64)paddr & DMA_BIT_MASK(32);
2495
-        RTL_W32(CounterAddrLow, cmd);
2496
-        RTL_W32(CounterAddrLow, cmd | CounterDump);
2497
+        RTL_W32(tp, CounterAddrLow, cmd);
2498
+        RTL_W32(tp, CounterAddrLow, cmd | CounterDump);
2499
 
2500
         WaitCnt = 0;
2501
-        while (RTL_R32(CounterAddrLow) & CounterDump) {
2502
+        while (RTL_R32(tp, CounterAddrLow) & CounterDump) {
2503
                 udelay(10);
2504
 
2505
                 WaitCnt++;
2506
@@ -5605,7 +5621,6 @@
2507
 
2508
 static int rtl8168_enable_EEE(struct rtl8168_private *tp)
2509
 {
2510
-        void __iomem *ioaddr = tp->mmio_addr;
2511
         int ret;
2512
         u16 data;
2513
         u32 csi_tmp;
2514
@@ -5630,10 +5645,10 @@
2515
                 rtl8168_mdio_write(tp, 0x0D, 0x4007);
2516
                 rtl8168_mdio_write(tp, 0x0E, 0x0006);
2517
                 rtl8168_mdio_write(tp, 0x0D, 0x0000);
2518
-                if ((RTL_R8(Config4)&0x40) && (RTL_R8(0x6D) & BIT_7)) {
2519
+                if ((RTL_R8(tp, Config4)&0x40) && (RTL_R8(tp, 0x6D) & BIT_7)) {
2520
                         rtl8168_mdio_write(tp, 0x1F, 0x0005);
2521
                         rtl8168_mdio_write(tp, 0x05, 0x8AC8);
2522
-                        rtl8168_mdio_write(tp, 0x06, RTL_R16(tp->NicCustLedValue));
2523
+                        rtl8168_mdio_write(tp, 0x06, RTL_R16(tp, tp->NicCustLedValue));
2524
                         rtl8168_mdio_write(tp, 0x05, 0x8B82);
2525
                         data = rtl8168_mdio_read(tp, 0x06) | 0x0010;
2526
                         rtl8168_mdio_write(tp, 0x05, 0x8B82);
2527
@@ -5644,8 +5659,8 @@
2528
 
2529
         case CFG_METHOD_16:
2530
         case CFG_METHOD_17:
2531
-                csi_tmp = rtl8168_eri_read(ioaddr, 0x1B0, 4, ERIAR_ExGMAC) | 0x0003;
2532
-                rtl8168_eri_write(ioaddr, 0x1B0, 4, csi_tmp, ERIAR_ExGMAC);
2533
+                csi_tmp = rtl8168_eri_read(tp, 0x1B0, 4, ERIAR_ExGMAC) | 0x0003;
2534
+                rtl8168_eri_write(tp, 0x1B0, 4, csi_tmp, ERIAR_ExGMAC);
2535
                 rtl8168_mdio_write(tp,0x1F , 0x0004);
2536
                 rtl8168_mdio_write(tp,0x1F , 0x0007);
2537
                 rtl8168_mdio_write(tp,0x1E , 0x0020);
2538
@@ -5667,9 +5682,9 @@
2539
         case CFG_METHOD_18:
2540
         case CFG_METHOD_19:
2541
         case CFG_METHOD_20:
2542
-                csi_tmp = rtl8168_eri_read(ioaddr, 0x1B0, 4, ERIAR_ExGMAC);
2543
+                csi_tmp = rtl8168_eri_read(tp, 0x1B0, 4, ERIAR_ExGMAC);
2544
                 csi_tmp |= BIT_1 | BIT_0;
2545
-                rtl8168_eri_write(ioaddr, 0x1B0, 4, csi_tmp, ERIAR_ExGMAC);
2546
+                rtl8168_eri_write(tp, 0x1B0, 4, csi_tmp, ERIAR_ExGMAC);
2547
                 rtl8168_mdio_write(tp, 0x1F, 0x0007);
2548
                 rtl8168_mdio_write(tp, 0x1e, 0x0020);
2549
                 data = rtl8168_mdio_read(tp, 0x15);
2550
@@ -5700,9 +5715,10 @@
2551
         case CFG_METHOD_30:
2552
         case CFG_METHOD_31:
2553
         case CFG_METHOD_32:
2554
-                csi_tmp = rtl8168_eri_read(ioaddr, 0x1B0, 4, ERIAR_ExGMAC);
2555
+        case CFG_METHOD_33:
2556
+                csi_tmp = rtl8168_eri_read(tp, 0x1B0, 4, ERIAR_ExGMAC);
2557
                 csi_tmp |= BIT_1 | BIT_0;
2558
-                rtl8168_eri_write(ioaddr, 0x1B0, 4, csi_tmp, ERIAR_ExGMAC);
2559
+                rtl8168_eri_write(tp, 0x1B0, 4, csi_tmp, ERIAR_ExGMAC);
2560
                 rtl8168_mdio_write(tp, 0x1F, 0x0A43);
2561
                 data = rtl8168_mdio_read(tp, 0x11);
2562
                 rtl8168_mdio_write(tp, 0x11, data | BIT_4);
2563
@@ -5722,6 +5738,7 @@
2564
         case CFG_METHOD_30:
2565
         case CFG_METHOD_31:
2566
         case CFG_METHOD_32:
2567
+        case CFG_METHOD_33:
2568
                 rtl8168_mdio_write(tp, 0x1F, 0x0A4A);
2569
                 rtl8168_set_eth_phy_bit(tp, 0x11, BIT_9);
2570
                 rtl8168_mdio_write(tp, 0x1F, 0x0A42);
2571
@@ -5737,6 +5754,7 @@
2572
         case CFG_METHOD_28:
2573
         case CFG_METHOD_31:
2574
         case CFG_METHOD_32:
2575
+        case CFG_METHOD_33:
2576
                 rtl8168_oob_mutex_lock(tp);
2577
                 break;
2578
         }
2579
@@ -5749,13 +5767,14 @@
2580
         case CFG_METHOD_30:
2581
         case CFG_METHOD_31:
2582
         case CFG_METHOD_32:
2583
+        case CFG_METHOD_33:
2584
                 rtl8168_set_phy_mcu_patch_request(tp);
2585
                 break;
2586
         }
2587
 
2588
         switch (tp->mcfg) {
2589
         case CFG_METHOD_25:
2590
-                rtl8168_eri_write(ioaddr, 0x1EA, 1, 0xFA, ERIAR_ExGMAC);
2591
+                rtl8168_eri_write(tp, 0x1EA, 1, 0xFA, ERIAR_ExGMAC);
2592
 
2593
                 rtl8168_mdio_write(tp, 0x1F, 0x0A43);
2594
                 data = rtl8168_mdio_read(tp, 0x10);
2595
@@ -5824,6 +5843,7 @@
2596
                 break;
2597
         case CFG_METHOD_31:
2598
         case CFG_METHOD_32:
2599
+        case CFG_METHOD_33:
2600
                 data = rtl8168_mac_ocp_read(tp, 0xE052);
2601
                 data |= BIT_0;
2602
                 rtl8168_mac_ocp_write(tp, 0xE052, data);
2603
@@ -5848,6 +5868,7 @@
2604
         case CFG_METHOD_30:
2605
         case CFG_METHOD_31:
2606
         case CFG_METHOD_32:
2607
+        case CFG_METHOD_33:
2608
                 rtl8168_clear_phy_mcu_patch_request(tp);
2609
                 break;
2610
         }
2611
@@ -5858,6 +5879,7 @@
2612
         case CFG_METHOD_28:
2613
         case CFG_METHOD_31:
2614
         case CFG_METHOD_32:
2615
+        case CFG_METHOD_33:
2616
                 rtl8168_oob_mutex_unlock(tp);
2617
                 break;
2618
         }
2619
@@ -5867,7 +5889,6 @@
2620
 
2621
 static int rtl8168_disable_EEE(struct rtl8168_private *tp)
2622
 {
2623
-        void __iomem *ioaddr = tp->mmio_addr;
2624
         int ret;
2625
         u16 data;
2626
         u32 csi_tmp;
2627
@@ -5893,7 +5914,7 @@
2628
                 rtl8168_mdio_write(tp, 0x0E, 0x0000);
2629
                 rtl8168_mdio_write(tp, 0x0D, 0x0000);
2630
                 rtl8168_mdio_write(tp, 0x1F, 0x0000);
2631
-                if (RTL_R8(Config4) & 0x40) {
2632
+                if (RTL_R8(tp, Config4) & 0x40) {
2633
                         rtl8168_mdio_write(tp, 0x1F, 0x0005);
2634
                         rtl8168_mdio_write(tp, 0x05, 0x8B82);
2635
                         data = rtl8168_mdio_read(tp, 0x06) & ~0x0010;
2636
@@ -5905,8 +5926,8 @@
2637
 
2638
         case CFG_METHOD_16:
2639
         case CFG_METHOD_17:
2640
-                csi_tmp = rtl8168_eri_read(ioaddr, 0x1B0,4, ERIAR_ExGMAC)& ~0x0003;
2641
-                rtl8168_eri_write(ioaddr, 0x1B0, 4, csi_tmp, ERIAR_ExGMAC);
2642
+                csi_tmp = rtl8168_eri_read(tp, 0x1B0,4, ERIAR_ExGMAC)& ~0x0003;
2643
+                rtl8168_eri_write(tp, 0x1B0, 4, csi_tmp, ERIAR_ExGMAC);
2644
                 rtl8168_mdio_write(tp, 0x1F, 0x0005);
2645
                 rtl8168_mdio_write(tp, 0x05, 0x8B85);
2646
                 data = rtl8168_mdio_read(tp, 0x06) & ~0x2000;
2647
@@ -5929,9 +5950,9 @@
2648
         case CFG_METHOD_18:
2649
         case CFG_METHOD_19:
2650
         case CFG_METHOD_20:
2651
-                csi_tmp = rtl8168_eri_read(ioaddr, 0x1B0, 4, ERIAR_ExGMAC);
2652
+                csi_tmp = rtl8168_eri_read(tp, 0x1B0, 4, ERIAR_ExGMAC);
2653
                 csi_tmp &= ~(BIT_1 | BIT_0);
2654
-                rtl8168_eri_write(ioaddr, 0x1B0, 4, csi_tmp, ERIAR_ExGMAC);
2655
+                rtl8168_eri_write(tp, 0x1B0, 4, csi_tmp, ERIAR_ExGMAC);
2656
                 rtl8168_mdio_write(tp, 0x1F, 0x0005);
2657
                 rtl8168_mdio_write(tp, 0x05, 0x8B85);
2658
                 data = rtl8168_mdio_read(tp, 0x06);
2659
@@ -5963,9 +5984,10 @@
2660
         case CFG_METHOD_30:
2661
         case CFG_METHOD_31:
2662
         case CFG_METHOD_32:
2663
-                csi_tmp = rtl8168_eri_read(ioaddr, 0x1B0, 4, ERIAR_ExGMAC);
2664
+        case CFG_METHOD_33:
2665
+                csi_tmp = rtl8168_eri_read(tp, 0x1B0, 4, ERIAR_ExGMAC);
2666
                 csi_tmp &= ~(BIT_1 | BIT_0);
2667
-                rtl8168_eri_write(ioaddr, 0x1B0, 4, csi_tmp, ERIAR_ExGMAC);
2668
+                rtl8168_eri_write(tp, 0x1B0, 4, csi_tmp, ERIAR_ExGMAC);
2669
                 rtl8168_mdio_write(tp, 0x1F, 0x0A43);
2670
                 data = rtl8168_mdio_read(tp, 0x11);
2671
                 rtl8168_mdio_write(tp, 0x11, data & ~BIT_4);
2672
@@ -5998,6 +6020,7 @@
2673
         case CFG_METHOD_28:
2674
         case CFG_METHOD_31:
2675
         case CFG_METHOD_32:
2676
+        case CFG_METHOD_33:
2677
                 rtl8168_oob_mutex_lock(tp);
2678
                 break;
2679
         }
2680
@@ -6010,13 +6033,14 @@
2681
         case CFG_METHOD_30:
2682
         case CFG_METHOD_31:
2683
         case CFG_METHOD_32:
2684
+        case CFG_METHOD_33:
2685
                 rtl8168_set_phy_mcu_patch_request(tp);
2686
                 break;
2687
         }
2688
 
2689
         switch (tp->mcfg) {
2690
         case CFG_METHOD_25:
2691
-                rtl8168_eri_write(ioaddr, 0x1EA, 1, 0x00, ERIAR_ExGMAC);
2692
+                rtl8168_eri_write(tp, 0x1EA, 1, 0x00, ERIAR_ExGMAC);
2693
 
2694
                 rtl8168_mdio_write(tp, 0x1F, 0x0A42);
2695
                 data = rtl8168_mdio_read(tp, 0x16);
2696
@@ -6045,6 +6069,7 @@
2697
         case CFG_METHOD_30:
2698
         case CFG_METHOD_31:
2699
         case CFG_METHOD_32:
2700
+        case CFG_METHOD_33:
2701
                 data = rtl8168_mac_ocp_read(tp, 0xE052);
2702
                 data &= ~(BIT_0);
2703
                 rtl8168_mac_ocp_write(tp, 0xE052, data);
2704
@@ -6068,6 +6093,7 @@
2705
         case CFG_METHOD_30:
2706
         case CFG_METHOD_31:
2707
         case CFG_METHOD_32:
2708
+        case CFG_METHOD_33:
2709
                 rtl8168_clear_phy_mcu_patch_request(tp);
2710
                 break;
2711
         }
2712
@@ -6078,6 +6104,7 @@
2713
         case CFG_METHOD_28:
2714
         case CFG_METHOD_31:
2715
         case CFG_METHOD_32:
2716
+        case CFG_METHOD_33:
2717
                 rtl8168_oob_mutex_unlock(tp);
2718
                 break;
2719
         }
2720
@@ -6091,11 +6118,13 @@
2721
         unsigned long flags;
2722
         int ret, bmcr;
2723
 
2724
-        if (unlikely(tp->rtk_enable_diag))
2725
-                return -EBUSY;
2726
-
2727
         spin_lock_irqsave(&tp->lock, flags);
2728
 
2729
+        if (unlikely(tp->rtk_enable_diag)) {
2730
+                spin_unlock_irqrestore(&tp->lock, flags);
2731
+                return -EBUSY;
2732
+        }
2733
+
2734
         /* if autoneg is off, it's an error */
2735
         rtl8168_mdio_write(tp, 0x1F, 0x0000);
2736
         bmcr = rtl8168_mdio_read(tp, MII_BMCR);
2737
@@ -6118,28 +6147,24 @@
2738
 rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *eee)
2739
 {
2740
         struct rtl8168_private *tp = netdev_priv(net);
2741
-        void __iomem *ioaddr = tp->mmio_addr;
2742
         u32 lp, adv, supported = 0;
2743
         unsigned long flags;
2744
         u16 val;
2745
 
2746
         switch (tp->mcfg) {
2747
-        case CFG_METHOD_27:
2748
-        case CFG_METHOD_28:
2749
-        case CFG_METHOD_29:
2750
-        case CFG_METHOD_30:
2751
-        case CFG_METHOD_31:
2752
-        case CFG_METHOD_32:
2753
+        case CFG_METHOD_21 ... CFG_METHOD_33:
2754
                 break;
2755
         default:
2756
                 return -EOPNOTSUPP;
2757
         }
2758
 
2759
-        if (unlikely(tp->rtk_enable_diag))
2760
-                return -EBUSY;
2761
-
2762
         spin_lock_irqsave(&tp->lock, flags);
2763
 
2764
+        if (unlikely(tp->rtk_enable_diag)) {
2765
+                spin_unlock_irqrestore(&tp->lock, flags);
2766
+                return -EBUSY;
2767
+        }
2768
+
2769
         rtl8168_mdio_write(tp, 0x1F, 0x0A5C);
2770
         val = rtl8168_mdio_read(tp, 0x12);
2771
         supported = mmd_eee_cap_to_ethtool_sup_t(val);
2772
@@ -6151,7 +6176,7 @@
2773
         val = rtl8168_mdio_read(tp, 0x11);
2774
         lp = mmd_eee_adv_to_ethtool_adv_t(val);
2775
 
2776
-        val = rtl8168_eri_read(ioaddr, 0x1B0, 2, ERIAR_ExGMAC);
2777
+        val = rtl8168_eri_read(tp, 0x1B0, 2, ERIAR_ExGMAC);
2778
         val &= BIT_1 | BIT_0;
2779
 
2780
         rtl8168_mdio_write(tp, 0x1F, 0x0000);
2781
@@ -6174,12 +6199,7 @@
2782
         unsigned long flags;
2783
 
2784
         switch (tp->mcfg) {
2785
-        case CFG_METHOD_27:
2786
-        case CFG_METHOD_28:
2787
-        case CFG_METHOD_29:
2788
-        case CFG_METHOD_30:
2789
-        case CFG_METHOD_31:
2790
-        case CFG_METHOD_32:
2791
+        case CFG_METHOD_21 ... CFG_METHOD_33:
2792
                 break;
2793
         default:
2794
                 return -EOPNOTSUPP;
2795
@@ -6321,6 +6341,7 @@
2796
         case CFG_METHOD_30:
2797
         case CFG_METHOD_31:
2798
         case CFG_METHOD_32:
2799
+        case CFG_METHOD_33:
2800
                 rtl8168_mdio_write(tp, 0x1F, 0x0A43);
2801
                 rtl8168_mdio_write(tp, 0x13, 0x8045);
2802
                 rtl8168_mdio_write(tp, 0x14, 0x0000);
2803
@@ -6398,6 +6419,7 @@
2804
         case CFG_METHOD_30:
2805
         case CFG_METHOD_31:
2806
         case CFG_METHOD_32:
2807
+        case CFG_METHOD_33:
2808
                 rtl8168_mdio_write(tp, 0x1F, 0x0A43);
2809
                 rtl8168_mdio_write(tp, 0x13, 0x8045);
2810
                 rtl8168_mdio_write(tp, 0x14, 0x2444);
2811
@@ -6421,12 +6443,12 @@
2812
 
2813
 #endif
2814
 
2815
-static void rtl8168_get_mac_version(struct rtl8168_private *tp, void __iomem *ioaddr)
2816
+static void rtl8168_get_mac_version(struct rtl8168_private *tp)
2817
 {
2818
         u32 reg,val32;
2819
         u32 ICVerID;
2820
 
2821
-        val32 = RTL_R32(TxConfig);
2822
+        val32 = RTL_R32(tp, TxConfig);
2823
         reg = val32 & 0x7c800000;
2824
         ICVerID = val32 & 0x00700000;
2825
 
2826
@@ -6486,7 +6508,7 @@
2827
                         tp->mcfg = CFG_METHOD_11;
2828
                 } else if (ICVerID == 0x00200000) {
2829
                         tp->mcfg = CFG_METHOD_12;
2830
-                        RTL_W32(0xD0, RTL_R32(0xD0) | 0x00020000);
2831
+                        RTL_W32(tp, 0xD0, RTL_R32(tp, 0xD0) | 0x00020000);
2832
                 } else if (ICVerID == 0x00300000) {
2833
                         tp->mcfg = CFG_METHOD_13;
2834
                 } else {
2835
@@ -6600,8 +6622,10 @@
2836
                         tp->mcfg = CFG_METHOD_31;
2837
                 } else if (ICVerID == 0x00200000) {
2838
                         tp->mcfg = CFG_METHOD_32;
2839
+                } else if (ICVerID == 0x00300000) {
2840
+                        tp->mcfg = CFG_METHOD_33;
2841
                 } else {
2842
-                        tp->mcfg = CFG_METHOD_32;
2843
+                        tp->mcfg = CFG_METHOD_33;
2844
                         tp->HwIcVerUnknown = TRUE;
2845
                 }
2846
 
2847
@@ -6680,7 +6704,6 @@
2848
 
2849
 static u8 rtl8168_efuse_read(struct rtl8168_private *tp, u16 reg)
2850
 {
2851
-        void __iomem *ioaddr = tp->mmio_addr;
2852
         u8 efuse_data = 0;
2853
         u32 temp;
2854
         int cnt;
2855
@@ -6690,36 +6713,36 @@
2856
 
2857
         if (tp->efuse_ver == EFUSE_SUPPORT_V1) {
2858
                 temp = EFUSE_READ | ((reg & EFUSE_Reg_Mask) << EFUSE_Reg_Shift);
2859
-                RTL_W32(EFUSEAR, temp);
2860
+                RTL_W32(tp, EFUSEAR, temp);
2861
 
2862
                 cnt = 0;
2863
                 do {
2864
                         udelay(100);
2865
-                        temp = RTL_R32(EFUSEAR);
2866
+                        temp = RTL_R32(tp, EFUSEAR);
2867
                         cnt++;
2868
                 } while (!(temp & EFUSE_READ_OK) && (cnt < EFUSE_Check_Cnt));
2869
 
2870
                 if (cnt == EFUSE_Check_Cnt)
2871
                         efuse_data = EFUSE_READ_FAIL;
2872
                 else
2873
-                        efuse_data = (u8)(RTL_R32(EFUSEAR) & EFUSE_Data_Mask);
2874
+                        efuse_data = (u8)(RTL_R32(tp, EFUSEAR) & EFUSE_Data_Mask);
2875
         } else  if (tp->efuse_ver == EFUSE_SUPPORT_V2) {
2876
                 temp = (reg/2) & 0x03ff;
2877
                 temp <<= 17;
2878
                 temp |= EFUSE_READ;
2879
-                RTL_W32(EFUSEAR, temp);
2880
+                RTL_W32(tp, EFUSEAR, temp);
2881
 
2882
                 cnt = 0;
2883
                 do {
2884
                         udelay(100);
2885
-                        temp = RTL_R32(EFUSEAR);
2886
+                        temp = RTL_R32(tp, EFUSEAR);
2887
                         cnt++;
2888
                 } while (!(temp & EFUSE_READ_OK) && (cnt < EFUSE_Check_Cnt));
2889
 
2890
                 if (cnt == EFUSE_Check_Cnt) {
2891
                         efuse_data = EFUSE_READ_FAIL;
2892
                 } else {
2893
-                        temp = RTL_R32(EFUSEAR);
2894
+                        temp = RTL_R32(tp, EFUSEAR);
2895
                         temp = rtl8168_decode_efuse_cmd(tp, temp);
2896
 
2897
                         if (reg%2) {
2898
@@ -6733,19 +6756,19 @@
2899
                 temp = (reg/2) & 0x03ff;
2900
                 temp <<= 16;
2901
                 temp |= EFUSE_READ_V3;
2902
-                RTL_W32(EFUSEAR, temp);
2903
+                RTL_W32(tp, EFUSEAR, temp);
2904
 
2905
                 cnt = 0;
2906
                 do {
2907
                         udelay(100);
2908
-                        temp = RTL_R32(EFUSEAR);
2909
+                        temp = RTL_R32(tp, EFUSEAR);
2910
                         cnt++;
2911
                 } while ((temp & BIT_31) && (cnt < EFUSE_Check_Cnt));
2912
 
2913
                 if (cnt == EFUSE_Check_Cnt) {
2914
                         efuse_data = EFUSE_READ_FAIL;
2915
                 } else {
2916
-                        temp = RTL_R32(EFUSEAR);
2917
+                        temp = RTL_R32(tp, EFUSEAR);
2918
                         temp = rtl8168_decode_efuse_cmd(tp, temp);
2919
 
2920
                         if (reg%2) {
2921
@@ -6765,20 +6788,16 @@
2922
 static void
2923
 rtl8168_tally_counter_addr_fill(struct rtl8168_private *tp)
2924
 {
2925
-        void __iomem *ioaddr = tp->mmio_addr;
2926
-
2927
         if (!tp->tally_paddr)
2928
                 return;
2929
 
2930
-        RTL_W32(CounterAddrHigh, (u64)tp->tally_paddr >> 32);
2931
-        RTL_W32(CounterAddrLow, (u64)tp->tally_paddr & (DMA_BIT_MASK(32)));
2932
+        RTL_W32(tp, CounterAddrHigh, (u64)tp->tally_paddr >> 32);
2933
+        RTL_W32(tp, CounterAddrLow, (u64)tp->tally_paddr & (DMA_BIT_MASK(32)));
2934
 }
2935
 
2936
 static void
2937
 rtl8168_tally_counter_clear(struct rtl8168_private *tp)
2938
 {
2939
-        void __iomem *ioaddr = tp->mmio_addr;
2940
-
2941
         if (tp->mcfg == CFG_METHOD_1 || tp->mcfg == CFG_METHOD_2 ||
2942
             tp->mcfg == CFG_METHOD_3 )
2943
                 return;
2944
@@ -6786,8 +6805,8 @@
2945
         if (!tp->tally_paddr)
2946
                 return;
2947
 
2948
-        RTL_W32(CounterAddrHigh, (u64)tp->tally_paddr >> 32);
2949
-        RTL_W32(CounterAddrLow, ((u64)tp->tally_paddr & (DMA_BIT_MASK(32))) | CounterReset);
2950
+        RTL_W32(tp, CounterAddrHigh, (u64)tp->tally_paddr >> 32);
2951
+        RTL_W32(tp, CounterAddrLow, ((u64)tp->tally_paddr & (DMA_BIT_MASK(32))) | CounterReset);
2952
 }
2953
 
2954
 static int
2955
@@ -6828,20 +6847,16 @@
2956
 void
2957
 rtl8168_enable_now_is_oob(struct rtl8168_private *tp)
2958
 {
2959
-        void __iomem *ioaddr = tp->mmio_addr;
2960
-
2961
         if ( tp->HwSuppNowIsOobVer == 1 ) {
2962
-                RTL_W8(MCUCmd_reg, RTL_R8(MCUCmd_reg) | Now_is_oob);
2963
+                RTL_W8(tp, MCUCmd_reg, RTL_R8(tp, MCUCmd_reg) | Now_is_oob);
2964
         }
2965
 }
2966
 
2967
 void
2968
 rtl8168_disable_now_is_oob(struct rtl8168_private *tp)
2969
 {
2970
-        void __iomem *ioaddr = tp->mmio_addr;
2971
-
2972
         if ( tp->HwSuppNowIsOobVer == 1 ) {
2973
-                RTL_W8(MCUCmd_reg, RTL_R8(MCUCmd_reg) & ~Now_is_oob);
2974
+                RTL_W8(tp, MCUCmd_reg, RTL_R8(tp, MCUCmd_reg) & ~Now_is_oob);
2975
         }
2976
 }
2977
 
2978
@@ -6849,10 +6864,9 @@
2979
 rtl8168_exit_oob(struct net_device *dev)
2980
 {
2981
         struct rtl8168_private *tp = netdev_priv(dev);
2982
-        void __iomem *ioaddr = tp->mmio_addr;
2983
         u16 data16;
2984
 
2985
-        RTL_W32(RxConfig, RTL_R32(RxConfig) & ~(AcceptErr | AcceptRunt | AcceptBroadcast | AcceptMulticast | AcceptMyPhys |  AcceptAllPhys));
2986
+        RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~(AcceptErr | AcceptRunt | AcceptBroadcast | AcceptMulticast | AcceptMyPhys |  AcceptAllPhys));
2987
 
2988
         switch (tp->mcfg) {
2989
         case CFG_METHOD_23:
2990
@@ -6860,12 +6874,12 @@
2991
         case CFG_METHOD_28:
2992
         case CFG_METHOD_31:
2993
         case CFG_METHOD_32:
2994
+        case CFG_METHOD_33:
2995
                 rtl8168_dash2_disable_txrx(dev);
2996
                 break;
2997
         }
2998
 
2999
-        if (tp->DASH) {
3000
-                rtl8168_driver_stop(tp);
3001
+        if (HW_DASH_SUPPORT_DASH(tp)) {
3002
                 rtl8168_driver_start(tp);
3003
 #ifdef ENABLE_DASH_SUPPORT
3004
                 DashHwInit(dev);
3005
@@ -6876,24 +6890,24 @@
3006
         switch (tp->mcfg) {
3007
         case CFG_METHOD_18:
3008
         case CFG_METHOD_19:
3009
-                RTL_W32(MACOCP, 0xE5A90000);
3010
-                RTL_W32(MACOCP, 0xF2100010);
3011
+                RTL_W32(tp, MACOCP, 0xE5A90000);
3012
+                RTL_W32(tp, MACOCP, 0xF2100010);
3013
                 break;
3014
         case CFG_METHOD_20:
3015
-                RTL_W32(MACOCP, 0xE5A90000);
3016
-                RTL_W32(MACOCP, 0xE4640000);
3017
-                RTL_W32(MACOCP, 0xF2100010);
3018
+                RTL_W32(tp, MACOCP, 0xE5A90000);
3019
+                RTL_W32(tp, MACOCP, 0xE4640000);
3020
+                RTL_W32(tp, MACOCP, 0xF2100010);
3021
                 break;
3022
         case CFG_METHOD_21:
3023
         case CFG_METHOD_22:
3024
-                RTL_W32(MACOCP, 0x605E0000);
3025
-                RTL_W32(MACOCP, (0xE05E << 16) | (RTL_R32(MACOCP) & 0xFFFE));
3026
-                RTL_W32(MACOCP, 0xE9720000);
3027
-                RTL_W32(MACOCP, 0xF2140010);
3028
+                RTL_W32(tp, MACOCP, 0x605E0000);
3029
+                RTL_W32(tp, MACOCP, (0xE05E << 16) | (RTL_R32(tp, MACOCP) & 0xFFFE));
3030
+                RTL_W32(tp, MACOCP, 0xE9720000);
3031
+                RTL_W32(tp, MACOCP, 0xF2140010);
3032
                 break;
3033
         case CFG_METHOD_26:
3034
-                RTL_W32(MACOCP, 0xE05E00FF);
3035
-                RTL_W32(MACOCP, 0xE9720000);
3036
+                RTL_W32(tp, MACOCP, 0xE05E00FF);
3037
+                RTL_W32(tp, MACOCP, 0xE9720000);
3038
                 rtl8168_mac_ocp_write(tp, 0xE428, 0x0010);
3039
                 break;
3040
         }
3041
@@ -6904,7 +6918,7 @@
3042
         switch (tp->mcfg) {
3043
         case CFG_METHOD_21:
3044
         case CFG_METHOD_22:
3045
-                rtl8168_eri_write(ioaddr, 0x174, 2, 0x0000, ERIAR_ExGMAC);
3046
+                rtl8168_eri_write(tp, 0x174, 2, 0x0000, ERIAR_ExGMAC);
3047
                 rtl8168_mac_ocp_write(tp, 0xE428, 0x0010);
3048
                 break;
3049
         case CFG_METHOD_24:
3050
@@ -6913,16 +6927,17 @@
3051
         case CFG_METHOD_28:
3052
         case CFG_METHOD_31:
3053
         case CFG_METHOD_32:
3054
-                rtl8168_eri_write(ioaddr, 0x174, 2, 0x00FF, ERIAR_ExGMAC);
3055
+        case CFG_METHOD_33:
3056
+                rtl8168_eri_write(tp, 0x174, 2, 0x00FF, ERIAR_ExGMAC);
3057
                 rtl8168_mac_ocp_write(tp, 0xE428, 0x0010);
3058
                 break;
3059
         case CFG_METHOD_29:
3060
         case CFG_METHOD_30: {
3061
                 u32 csi_tmp;
3062
-                csi_tmp = rtl8168_eri_read(ioaddr, 0x174, 2, ERIAR_ExGMAC);
3063
+                csi_tmp = rtl8168_eri_read(tp, 0x174, 2, ERIAR_ExGMAC);
3064
                 csi_tmp &= ~(BIT_8);
3065
                 csi_tmp |= (BIT_15);
3066
-                rtl8168_eri_write(ioaddr, 0x174, 2, csi_tmp, ERIAR_ExGMAC);
3067
+                rtl8168_eri_write(tp, 0x174, 2, csi_tmp, ERIAR_ExGMAC);
3068
                 rtl8168_mac_ocp_write(tp, 0xE428, 0x0010);
3069
         }
3070
         break;
3071
@@ -6952,6 +6967,7 @@
3072
         case CFG_METHOD_30:
3073
         case CFG_METHOD_31:
3074
         case CFG_METHOD_32:
3075
+        case CFG_METHOD_33:
3076
                 rtl8168_disable_now_is_oob(tp);
3077
 
3078
                 data16 = rtl8168_mac_ocp_read(tp, 0xE8DE) & ~BIT_14;
3079
@@ -6971,6 +6987,7 @@
3080
         case CFG_METHOD_30:
3081
         case CFG_METHOD_31:
3082
         case CFG_METHOD_32:
3083
+        case CFG_METHOD_33:
3084
                 if (rtl8168_is_ups_resume(dev)) {
3085
                         rtl8168_wait_phy_ups_resume(dev, 2);
3086
                         rtl8168_clear_ups_resume_bit(dev);
3087
@@ -6990,7 +7007,6 @@
3088
 rtl8168_hw_disable_mac_mcu_bps(struct net_device *dev)
3089
 {
3090
         struct rtl8168_private *tp = netdev_priv(dev);
3091
-        void __iomem *ioaddr = tp->mmio_addr;
3092
 
3093
         switch (tp->mcfg) {
3094
         case CFG_METHOD_21:
3095
@@ -7005,9 +7021,10 @@
3096
         case CFG_METHOD_30:
3097
         case CFG_METHOD_31:
3098
         case CFG_METHOD_32:
3099
+        case CFG_METHOD_33:
3100
                 rtl8168_enable_cfg9346_write(tp);
3101
-                RTL_W8(Config5, RTL_R8(Config5) & ~BIT_0);
3102
-                RTL_W8(Config2, RTL_R8(Config2) & ~BIT_7);
3103
+                RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~BIT_0);
3104
+                RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~BIT_7);
3105
                 rtl8168_disable_cfg9346_write(tp);
3106
                 break;
3107
         }
3108
@@ -7017,6 +7034,7 @@
3109
         case CFG_METHOD_30:
3110
         case CFG_METHOD_31:
3111
         case CFG_METHOD_32:
3112
+        case CFG_METHOD_33:
3113
                 rtl8168_mac_ocp_write(tp, 0xFC38, 0x0000);
3114
                 break;
3115
         }
3116
@@ -7034,6 +7052,7 @@
3117
         case CFG_METHOD_30:
3118
         case CFG_METHOD_31:
3119
         case CFG_METHOD_32:
3120
+        case CFG_METHOD_33:
3121
                 rtl8168_mac_ocp_write(tp, 0xFC28, 0x0000);
3122
                 rtl8168_mac_ocp_write(tp, 0xFC2A, 0x0000);
3123
                 rtl8168_mac_ocp_write(tp, 0xFC2C, 0x0000);
3124
@@ -9198,6 +9217,12 @@
3125
 }
3126
 
3127
 static void
3128
+rtl8168_set_mac_mcu_8168fp_4(struct net_device *dev)
3129
+{
3130
+        rtl8168_hw_disable_mac_mcu_bps(dev);
3131
+}
3132
+
3133
+static void
3134
 rtl8168_hw_mac_mcu_config(struct net_device *dev)
3135
 {
3136
         struct rtl8168_private *tp = netdev_priv(dev);
3137
@@ -9236,6 +9261,9 @@
3138
         case CFG_METHOD_32:
3139
                 rtl8168_set_mac_mcu_8168fp_3(dev);
3140
                 break;
3141
+        case CFG_METHOD_33:
3142
+                rtl8168_set_mac_mcu_8168fp_4(dev);
3143
+                break;
3144
         }
3145
 }
3146
 
3147
@@ -9243,7 +9271,6 @@
3148
 rtl8168_hw_init(struct net_device *dev)
3149
 {
3150
         struct rtl8168_private *tp = netdev_priv(dev);
3151
-        void __iomem *ioaddr = tp->mmio_addr;
3152
         u32 csi_tmp;
3153
 
3154
         switch (tp->mcfg) {
3155
@@ -9266,11 +9293,12 @@
3156
         case CFG_METHOD_30:
3157
         case CFG_METHOD_31:
3158
         case CFG_METHOD_32:
3159
+        case CFG_METHOD_33:
3160
                 rtl8168_enable_cfg9346_write(tp);
3161
-                RTL_W8(Config5, RTL_R8(Config5) & ~BIT_0);
3162
-                RTL_W8(Config2, RTL_R8(Config2) & ~BIT_7);
3163
+                RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~BIT_0);
3164
+                RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~BIT_7);
3165
                 rtl8168_disable_cfg9346_write(tp);
3166
-                RTL_W8(0xF1, RTL_R8(0xF1) & ~BIT_7);
3167
+                RTL_W8(tp, 0xF1, RTL_R8(tp, 0xF1) & ~BIT_7);
3168
                 break;
3169
         }
3170
 
3171
@@ -9280,6 +9308,7 @@
3172
         case CFG_METHOD_30:
3173
         case CFG_METHOD_31:
3174
         case CFG_METHOD_32:
3175
+        case CFG_METHOD_33:
3176
                 rtl8168_mac_ocp_write(tp, 0xD400, rtl8168_mac_ocp_read( tp, 0xD400) & ~(BIT_0));
3177
                 break;
3178
         }
3179
@@ -9290,6 +9319,7 @@
3180
         case CFG_METHOD_30:
3181
         case CFG_METHOD_31:
3182
         case CFG_METHOD_32:
3183
+        case CFG_METHOD_33:
3184
                 rtl8168_mac_ocp_write(tp, 0xE63E, rtl8168_mac_ocp_read( tp, 0xE63E) & ~(BIT_3 | BIT_2 | BIT_1));
3185
                 rtl8168_mac_ocp_write(tp, 0xE63E, rtl8168_mac_ocp_read( tp, 0xE63E) | (BIT_0));
3186
                 rtl8168_mac_ocp_write(tp, 0xE63E, rtl8168_mac_ocp_read( tp, 0xE63E) & ~(BIT_0));
3187
@@ -9301,7 +9331,7 @@
3188
         switch (tp->mcfg) {
3189
         case CFG_METHOD_9:
3190
         case CFG_METHOD_10:
3191
-                RTL_W8(DBG_reg, RTL_R8(DBG_reg) | BIT_1 | BIT_7);
3192
+                RTL_W8(tp, DBG_reg, RTL_R8(tp, DBG_reg) | BIT_1 | BIT_7);
3193
                 break;
3194
         }
3195
 
3196
@@ -9312,7 +9342,7 @@
3197
         case CFG_METHOD_17:
3198
         case CFG_METHOD_18:
3199
         case CFG_METHOD_19:
3200
-                RTL_W8(0xF2, (RTL_R8(0xF2) & ~(BIT_2 | BIT_1 | BIT_0)));
3201
+                RTL_W8(tp, 0xF2, (RTL_R8(tp, 0xF2) & ~(BIT_2 | BIT_1 | BIT_0)));
3202
                 break;
3203
         }
3204
 
3205
@@ -9323,8 +9353,8 @@
3206
         case CFG_METHOD_19:
3207
         case CFG_METHOD_20:
3208
                 if (aspm) {
3209
-                        RTL_W8(0x6E, RTL_R8(0x6E) | BIT_6);
3210
-                        rtl8168_eri_write(ioaddr, 0x1AE, 2, 0x0403, ERIAR_ExGMAC);
3211
+                        RTL_W8(tp, 0x6E, RTL_R8(tp, 0x6E) | BIT_6);
3212
+                        rtl8168_eri_write(tp, 0x1AE, 2, 0x0403, ERIAR_ExGMAC);
3213
                 }
3214
                 break;
3215
         case CFG_METHOD_21:
3216
@@ -9332,16 +9362,16 @@
3217
         case CFG_METHOD_29:
3218
         case CFG_METHOD_30:
3219
                 if (aspm) {
3220
-                        if ((rtl8168_mac_ocp_read(tp, 0xDC00) & BIT_3) || (RTL_R8(Config0) & 0x07)) {
3221
-                                RTL_W8(0x6E, RTL_R8(0x6E) | BIT_6);
3222
-                                rtl8168_eri_write(ioaddr, 0x1AE, 2, 0x0403, ERIAR_ExGMAC);
3223
+                        if ((rtl8168_mac_ocp_read(tp, 0xDC00) & BIT_3) || (RTL_R8(tp, Config0) & 0x07)) {
3224
+                                RTL_W8(tp, 0x6E, RTL_R8(tp, 0x6E) | BIT_6);
3225
+                                rtl8168_eri_write(tp, 0x1AE, 2, 0x0403, ERIAR_ExGMAC);
3226
                         }
3227
                 }
3228
                 break;
3229
         }
3230
 
3231
         if (tp->mcfg == CFG_METHOD_10 || tp->mcfg == CFG_METHOD_14 || tp->mcfg == CFG_METHOD_15)
3232
-                RTL_W8(0xF3, RTL_R8(0xF3) | BIT_2);
3233
+                RTL_W8(tp, 0xF3, RTL_R8(tp, 0xF3) | BIT_2);
3234
 
3235
         rtl8168_hw_mac_mcu_config(dev);
3236
 
3237
@@ -9349,7 +9379,8 @@
3238
         if (tp->mcfg == CFG_METHOD_25 || tp->mcfg == CFG_METHOD_26 ||
3239
             tp->mcfg == CFG_METHOD_27 || tp->mcfg == CFG_METHOD_28 ||
3240
             tp->mcfg == CFG_METHOD_29 || tp->mcfg == CFG_METHOD_30 ||
3241
-            tp->mcfg == CFG_METHOD_31 || tp->mcfg == CFG_METHOD_32)
3242
+            tp->mcfg == CFG_METHOD_31 || tp->mcfg == CFG_METHOD_32 ||
3243
+            tp->mcfg == CFG_METHOD_33)
3244
                 if (!tp->dash_printer_enabled)
3245
                         rtl8168_disable_ocp_phy_power_saving(dev);
3246
 
3247
@@ -9363,9 +9394,9 @@
3248
         case CFG_METHOD_22:
3249
         case CFG_METHOD_23:
3250
         case CFG_METHOD_24:
3251
-                csi_tmp = rtl8168_eri_read(ioaddr, 0x1AB, 1, ERIAR_ExGMAC);
3252
+                csi_tmp = rtl8168_eri_read(tp, 0x1AB, 1, ERIAR_ExGMAC);
3253
                 csi_tmp |= ( BIT_2 | BIT_3 | BIT_4 | BIT_5 | BIT_6 | BIT_7 );
3254
-                rtl8168_eri_write(ioaddr, 0x1AB, 1, csi_tmp, ERIAR_ExGMAC);
3255
+                rtl8168_eri_write(tp, 0x1AB, 1, csi_tmp, ERIAR_ExGMAC);
3256
                 break;
3257
         }
3258
 
3259
@@ -9377,27 +9408,26 @@
3260
 rtl8168_hw_ephy_config(struct net_device *dev)
3261
 {
3262
         struct rtl8168_private *tp = netdev_priv(dev);
3263
-        void __iomem *ioaddr = tp->mmio_addr;
3264
         u16 ephy_data;
3265
 
3266
         switch (tp->mcfg) {
3267
         case CFG_METHOD_4:
3268
                 /*Set EPHY registers    begin*/
3269
                 /*Set EPHY register offset 0x02 bit 11 to 0 and bit 12 to 1*/
3270
-                ephy_data = rtl8168_ephy_read(ioaddr, 0x02);
3271
+                ephy_data = rtl8168_ephy_read(tp, 0x02);
3272
                 ephy_data &= ~BIT_11;
3273
                 ephy_data |= BIT_12;
3274
-                rtl8168_ephy_write(ioaddr, 0x02, ephy_data);
3275
+                rtl8168_ephy_write(tp, 0x02, ephy_data);
3276
 
3277
                 /*Set EPHY register offset 0x03 bit 1 to 1*/
3278
-                ephy_data = rtl8168_ephy_read(ioaddr, 0x03);
3279
+                ephy_data = rtl8168_ephy_read(tp, 0x03);
3280
                 ephy_data |= (1 << 1);
3281
-                rtl8168_ephy_write(ioaddr, 0x03, ephy_data);
3282
+                rtl8168_ephy_write(tp, 0x03, ephy_data);
3283
 
3284
                 /*Set EPHY register offset 0x06 bit 7 to 0*/
3285
-                ephy_data = rtl8168_ephy_read(ioaddr, 0x06);
3286
+                ephy_data = rtl8168_ephy_read(tp, 0x06);
3287
                 ephy_data &= ~(1 << 7);
3288
-                rtl8168_ephy_write(ioaddr, 0x06, ephy_data);
3289
+                rtl8168_ephy_write(tp, 0x06, ephy_data);
3290
                 /*Set EPHY registers    end*/
3291
 
3292
                 break;
3293
@@ -9414,8 +9444,8 @@
3294
                 break;
3295
         case CFG_METHOD_9:
3296
                 /* set EPHY registers */
3297
-                rtl8168_ephy_write(ioaddr, 0x01, 0x7C7F);
3298
-                rtl8168_ephy_write(ioaddr, 0x02, 0x011F);
3299
+                rtl8168_ephy_write(tp, 0x01, 0x7C7F);
3300
+                rtl8168_ephy_write(tp, 0x02, 0x011F);
3301
                 if (tp->eeprom_type != EEPROM_TYPE_NONE) {
3302
                         ClearAndSetPCIePhyBit(tp,
3303
                                               0x03,
3304
@@ -9429,210 +9459,210 @@
3305
                                               0x05F0
3306
                                              );
3307
                 }
3308
-                rtl8168_ephy_write(ioaddr, 0x06, 0xB271);
3309
-                rtl8168_ephy_write(ioaddr, 0x07, 0xCE00);
3310
+                rtl8168_ephy_write(tp, 0x06, 0xB271);
3311
+                rtl8168_ephy_write(tp, 0x07, 0xCE00);
3312
 
3313
                 break;
3314
         case CFG_METHOD_10:
3315
                 /* set EPHY registers */
3316
-                rtl8168_ephy_write(ioaddr, 0x01, 0x6C7F);
3317
-                rtl8168_ephy_write(ioaddr, 0x02, 0x011F);
3318
+                rtl8168_ephy_write(tp, 0x01, 0x6C7F);
3319
+                rtl8168_ephy_write(tp, 0x02, 0x011F);
3320
                 ClearAndSetPCIePhyBit(tp,
3321
                                       0x03,
3322
                                       0xFFF0,
3323
                                       0x01B0
3324
                                      );
3325
-                rtl8168_ephy_write(ioaddr, 0x1A, 0x0546);
3326
-                rtl8168_ephy_write(ioaddr, 0x1C, 0x80C4);
3327
-                rtl8168_ephy_write(ioaddr, 0x1D, 0x78E5);
3328
-                rtl8168_ephy_write(ioaddr, 0x0A, 0x8100);
3329
+                rtl8168_ephy_write(tp, 0x1A, 0x0546);
3330
+                rtl8168_ephy_write(tp, 0x1C, 0x80C4);
3331
+                rtl8168_ephy_write(tp, 0x1D, 0x78E5);
3332
+                rtl8168_ephy_write(tp, 0x0A, 0x8100);
3333
 
3334
                 break;
3335
         case CFG_METHOD_12:
3336
         case CFG_METHOD_13:
3337
-                ephy_data = rtl8168_ephy_read(ioaddr, 0x0B);
3338
-                rtl8168_ephy_write(ioaddr, 0x0B, ephy_data|0x48);
3339
-                ephy_data = rtl8168_ephy_read(ioaddr, 0x19);
3340
+                ephy_data = rtl8168_ephy_read(tp, 0x0B);
3341
+                rtl8168_ephy_write(tp, 0x0B, ephy_data|0x48);
3342
+                ephy_data = rtl8168_ephy_read(tp, 0x19);
3343
                 ephy_data &= ~0x20;
3344
-                rtl8168_ephy_write(ioaddr, 0x19, ephy_data|0x50);
3345
-                ephy_data = rtl8168_ephy_read(ioaddr, 0x0C);
3346
+                rtl8168_ephy_write(tp, 0x19, ephy_data|0x50);
3347
+                ephy_data = rtl8168_ephy_read(tp, 0x0C);
3348
                 ephy_data &= ~0x100;
3349
-                rtl8168_ephy_write(ioaddr, 0x0C, ephy_data|0x20);
3350
-                ephy_data = rtl8168_ephy_read(ioaddr, 0x10);
3351
+                rtl8168_ephy_write(tp, 0x0C, ephy_data|0x20);
3352
+                ephy_data = rtl8168_ephy_read(tp, 0x10);
3353
                 ephy_data &= ~0x04;
3354
-                rtl8168_ephy_write(ioaddr, 0x10, ephy_data);
3355
+                rtl8168_ephy_write(tp, 0x10, ephy_data);
3356
 
3357
                 break;
3358
         case CFG_METHOD_14:
3359
         case CFG_METHOD_15:
3360
                 /* set EPHY registers */
3361
-                ephy_data = rtl8168_ephy_read(ioaddr, 0x00) & ~0x0200;
3362
+                ephy_data = rtl8168_ephy_read(tp, 0x00) & ~0x0200;
3363
                 ephy_data |= 0x0100;
3364
-                rtl8168_ephy_write(ioaddr, 0x00, ephy_data);
3365
+                rtl8168_ephy_write(tp, 0x00, ephy_data);
3366
 
3367
-                ephy_data = rtl8168_ephy_read(ioaddr, 0x00);
3368
+                ephy_data = rtl8168_ephy_read(tp, 0x00);
3369
                 ephy_data |= 0x0004;
3370
-                rtl8168_ephy_write(ioaddr, 0x00, ephy_data);
3371
+                rtl8168_ephy_write(tp, 0x00, ephy_data);
3372
 
3373
-                ephy_data = rtl8168_ephy_read(ioaddr, 0x06) & ~0x0002;
3374
+                ephy_data = rtl8168_ephy_read(tp, 0x06) & ~0x0002;
3375
                 ephy_data |= 0x0001;
3376
-                rtl8168_ephy_write(ioaddr, 0x06, ephy_data);
3377
+                rtl8168_ephy_write(tp, 0x06, ephy_data);
3378
 
3379
-                ephy_data = rtl8168_ephy_read(ioaddr, 0x06);
3380
+                ephy_data = rtl8168_ephy_read(tp, 0x06);
3381
                 ephy_data |= 0x0030;
3382
-                rtl8168_ephy_write(ioaddr, 0x06, ephy_data);
3383
+                rtl8168_ephy_write(tp, 0x06, ephy_data);
3384
 
3385
-                ephy_data = rtl8168_ephy_read(ioaddr, 0x07);
3386
+                ephy_data = rtl8168_ephy_read(tp, 0x07);
3387
                 ephy_data |= 0x2000;
3388
-                rtl8168_ephy_write(ioaddr, 0x07, ephy_data);
3389
+                rtl8168_ephy_write(tp, 0x07, ephy_data);
3390
 
3391
-                ephy_data = rtl8168_ephy_read(ioaddr, 0x00);
3392
+                ephy_data = rtl8168_ephy_read(tp, 0x00);
3393
                 ephy_data |= 0x0020;
3394
-                rtl8168_ephy_write(ioaddr, 0x00, ephy_data);
3395
+                rtl8168_ephy_write(tp, 0x00, ephy_data);
3396
 
3397
-                ephy_data = rtl8168_ephy_read(ioaddr, 0x03) & ~0x5800;
3398
+                ephy_data = rtl8168_ephy_read(tp, 0x03) & ~0x5800;
3399
                 ephy_data |= 0x2000;
3400
-                rtl8168_ephy_write(ioaddr, 0x03, ephy_data);
3401
+                rtl8168_ephy_write(tp, 0x03, ephy_data);
3402
 
3403
-                ephy_data = rtl8168_ephy_read(ioaddr, 0x03);
3404
+                ephy_data = rtl8168_ephy_read(tp, 0x03);
3405
                 ephy_data |= 0x0001;
3406
-                rtl8168_ephy_write(ioaddr, 0x03, ephy_data);
3407
+                rtl8168_ephy_write(tp, 0x03, ephy_data);
3408
 
3409
-                ephy_data = rtl8168_ephy_read(ioaddr, 0x01) & ~0x0800;
3410
+                ephy_data = rtl8168_ephy_read(tp, 0x01) & ~0x0800;
3411
                 ephy_data |= 0x1000;
3412
-                rtl8168_ephy_write(ioaddr, 0x01, ephy_data);
3413
+                rtl8168_ephy_write(tp, 0x01, ephy_data);
3414
 
3415
-                ephy_data = rtl8168_ephy_read(ioaddr, 0x07);
3416
+                ephy_data = rtl8168_ephy_read(tp, 0x07);
3417
                 ephy_data |= 0x4000;
3418
-                rtl8168_ephy_write(ioaddr, 0x07, ephy_data);
3419
+                rtl8168_ephy_write(tp, 0x07, ephy_data);
3420
 
3421
-                ephy_data = rtl8168_ephy_read(ioaddr, 0x1E);
3422
+                ephy_data = rtl8168_ephy_read(tp, 0x1E);
3423
                 ephy_data |= 0x2000;
3424
-                rtl8168_ephy_write(ioaddr, 0x1E, ephy_data);
3425
+                rtl8168_ephy_write(tp, 0x1E, ephy_data);
3426
 
3427
-                rtl8168_ephy_write(ioaddr, 0x19, 0xFE6C);
3428
+                rtl8168_ephy_write(tp, 0x19, 0xFE6C);
3429
 
3430
-                ephy_data = rtl8168_ephy_read(ioaddr, 0x0A);
3431
+                ephy_data = rtl8168_ephy_read(tp, 0x0A);
3432
                 ephy_data |= 0x0040;
3433
-                rtl8168_ephy_write(ioaddr, 0x0A, ephy_data);
3434
+                rtl8168_ephy_write(tp, 0x0A, ephy_data);
3435
 
3436
                 break;
3437
         case CFG_METHOD_16:
3438
         case CFG_METHOD_17:
3439
                 if (tp->mcfg == CFG_METHOD_16) {
3440
-                        rtl8168_ephy_write(ioaddr, 0x06, 0xF020);
3441
-                        rtl8168_ephy_write(ioaddr, 0x07, 0x01FF);
3442
-                        rtl8168_ephy_write(ioaddr, 0x00, 0x5027);
3443
-                        rtl8168_ephy_write(ioaddr, 0x01, 0x0003);
3444
-                        rtl8168_ephy_write(ioaddr, 0x02, 0x2D16);
3445
-                        rtl8168_ephy_write(ioaddr, 0x03, 0x6D49);
3446
-                        rtl8168_ephy_write(ioaddr, 0x08, 0x0006);
3447
-                        rtl8168_ephy_write(ioaddr, 0x0A, 0x00C8);
3448
+                        rtl8168_ephy_write(tp, 0x06, 0xF020);
3449
+                        rtl8168_ephy_write(tp, 0x07, 0x01FF);
3450
+                        rtl8168_ephy_write(tp, 0x00, 0x5027);
3451
+                        rtl8168_ephy_write(tp, 0x01, 0x0003);
3452
+                        rtl8168_ephy_write(tp, 0x02, 0x2D16);
3453
+                        rtl8168_ephy_write(tp, 0x03, 0x6D49);
3454
+                        rtl8168_ephy_write(tp, 0x08, 0x0006);
3455
+                        rtl8168_ephy_write(tp, 0x0A, 0x00C8);
3456
                 }
3457
 
3458
-                ephy_data = rtl8168_ephy_read(ioaddr, 0x09);
3459
+                ephy_data = rtl8168_ephy_read(tp, 0x09);
3460
                 ephy_data |= BIT_7;
3461
-                rtl8168_ephy_write(ioaddr, 0x09, ephy_data);
3462
+                rtl8168_ephy_write(tp, 0x09, ephy_data);
3463
 
3464
-                ephy_data = rtl8168_ephy_read(ioaddr, 0x19);
3465
+                ephy_data = rtl8168_ephy_read(tp, 0x19);
3466
                 ephy_data |= (BIT_2 | BIT_5 | BIT_9);
3467
-                rtl8168_ephy_write(ioaddr, 0x19, ephy_data);
3468
+                rtl8168_ephy_write(tp, 0x19, ephy_data);
3469
 
3470
-                ephy_data = rtl8168_ephy_read(ioaddr, 0x00);
3471
+                ephy_data = rtl8168_ephy_read(tp, 0x00);
3472
                 ephy_data |= BIT_3;
3473
-                rtl8168_ephy_write(ioaddr, 0x00, ephy_data);
3474
-                ephy_data = rtl8168_ephy_read(ioaddr, 0x0C);
3475
+                rtl8168_ephy_write(tp, 0x00, ephy_data);
3476
+                ephy_data = rtl8168_ephy_read(tp, 0x0C);
3477
                 ephy_data &= ~(BIT_13 | BIT_12 | BIT_11 | BIT_10 | BIT_8 | BIT_7 | BIT_6 | BIT_5 | BIT_4);
3478
                 ephy_data |= BIT_9;
3479
-                rtl8168_ephy_write(ioaddr, 0x0C, ephy_data);
3480
+                rtl8168_ephy_write(tp, 0x0C, ephy_data);
3481
 
3482
                 break;
3483
         case CFG_METHOD_18:
3484
         case CFG_METHOD_19:
3485
                 if (tp->mcfg == CFG_METHOD_18) {
3486
-                        ephy_data = rtl8168_ephy_read(ioaddr, 0x06);
3487
+                        ephy_data = rtl8168_ephy_read(tp, 0x06);
3488
                         ephy_data |= BIT_5;
3489
                         ephy_data &= ~(BIT_7 | BIT_6);
3490
-                        rtl8168_ephy_write(ioaddr, 0x06, ephy_data);
3491
+                        rtl8168_ephy_write(tp, 0x06, ephy_data);
3492
 
3493
-                        ephy_data = rtl8168_ephy_read(ioaddr, 0x08);
3494
+                        ephy_data = rtl8168_ephy_read(tp, 0x08);
3495
                         ephy_data |= BIT_1;
3496
                         ephy_data &= ~BIT_0;
3497
-                        rtl8168_ephy_write(ioaddr, 0x08, ephy_data);
3498
+                        rtl8168_ephy_write(tp, 0x08, ephy_data);
3499
                 }
3500
 
3501
-                ephy_data = rtl8168_ephy_read(ioaddr, 0x09);
3502
+                ephy_data = rtl8168_ephy_read(tp, 0x09);
3503
                 ephy_data |= BIT_7;
3504
-                rtl8168_ephy_write(ioaddr, 0x09, ephy_data);
3505
+                rtl8168_ephy_write(tp, 0x09, ephy_data);
3506
 
3507
-                ephy_data = rtl8168_ephy_read(ioaddr, 0x19);
3508
+                ephy_data = rtl8168_ephy_read(tp, 0x19);
3509
                 ephy_data |= (BIT_2 | BIT_5 | BIT_9);
3510
-                rtl8168_ephy_write(ioaddr, 0x19, ephy_data);
3511
+                rtl8168_ephy_write(tp, 0x19, ephy_data);
3512
 
3513
-                ephy_data = rtl8168_ephy_read(ioaddr, 0x00);
3514
+                ephy_data = rtl8168_ephy_read(tp, 0x00);
3515
                 ephy_data |= BIT_3;
3516
-                rtl8168_ephy_write(ioaddr, 0x00, ephy_data);
3517
-                ephy_data = rtl8168_ephy_read(ioaddr, 0x0C);
3518
+                rtl8168_ephy_write(tp, 0x00, ephy_data);
3519
+                ephy_data = rtl8168_ephy_read(tp, 0x0C);
3520
                 ephy_data &= ~(BIT_13 | BIT_12 | BIT_11 | BIT_10 | BIT_8 | BIT_7 | BIT_6 | BIT_5 | BIT_4);
3521
                 ephy_data |= BIT_9;
3522
-                rtl8168_ephy_write(ioaddr, 0x0C, ephy_data);
3523
+                rtl8168_ephy_write(tp, 0x0C, ephy_data);
3524
 
3525
                 break;
3526
         case CFG_METHOD_20:
3527
-                ephy_data = rtl8168_ephy_read(ioaddr, 0x06);
3528
+                ephy_data = rtl8168_ephy_read(tp, 0x06);
3529
                 ephy_data |= BIT_5;
3530
                 ephy_data &= ~(BIT_7 | BIT_6);
3531
-                rtl8168_ephy_write(ioaddr, 0x06, ephy_data);
3532
+                rtl8168_ephy_write(tp, 0x06, ephy_data);
3533
 
3534
-                rtl8168_ephy_write(ioaddr, 0x0f, 0x5200);
3535
+                rtl8168_ephy_write(tp, 0x0f, 0x5200);
3536
 
3537
-                ephy_data = rtl8168_ephy_read(ioaddr, 0x19);
3538
+                ephy_data = rtl8168_ephy_read(tp, 0x19);
3539
                 ephy_data |= (BIT_2 | BIT_5 | BIT_9);
3540
-                rtl8168_ephy_write(ioaddr, 0x19, ephy_data);
3541
+                rtl8168_ephy_write(tp, 0x19, ephy_data);
3542
 
3543
-                ephy_data = rtl8168_ephy_read(ioaddr, 0x00);
3544
+                ephy_data = rtl8168_ephy_read(tp, 0x00);
3545
                 ephy_data |= BIT_3;
3546
-                rtl8168_ephy_write(ioaddr, 0x00, ephy_data);
3547
-                ephy_data = rtl8168_ephy_read(ioaddr, 0x0C);
3548
+                rtl8168_ephy_write(tp, 0x00, ephy_data);
3549
+                ephy_data = rtl8168_ephy_read(tp, 0x0C);
3550
                 ephy_data &= ~(BIT_13 | BIT_12 | BIT_11 | BIT_10 | BIT_8 | BIT_7 | BIT_6 | BIT_5 | BIT_4);
3551
                 ephy_data |= BIT_9;
3552
-                rtl8168_ephy_write(ioaddr, 0x0C, ephy_data);
3553
+                rtl8168_ephy_write(tp, 0x0C, ephy_data);
3554
 
3555
                 break;
3556
         case CFG_METHOD_21:
3557
         case CFG_METHOD_22:
3558
 
3559
-                ephy_data = rtl8168_ephy_read(ioaddr, 0x00);
3560
+                ephy_data = rtl8168_ephy_read(tp, 0x00);
3561
                 ephy_data &= ~(BIT_3);
3562
-                rtl8168_ephy_write(ioaddr, 0x00, ephy_data);
3563
-                ephy_data = rtl8168_ephy_read(ioaddr, 0x0C);
3564
+                rtl8168_ephy_write(tp, 0x00, ephy_data);
3565
+                ephy_data = rtl8168_ephy_read(tp, 0x0C);
3566
                 ephy_data &= ~(BIT_13 | BIT_12 | BIT_11 | BIT_10 | BIT_9 | BIT_8 | BIT_7 | BIT_6 | BIT_5 | BIT_4);
3567
                 ephy_data |= (BIT_5 | BIT_11);
3568
-                rtl8168_ephy_write(ioaddr, 0x0C, ephy_data);
3569
+                rtl8168_ephy_write(tp, 0x0C, ephy_data);
3570
 
3571
-                ephy_data = rtl8168_ephy_read(ioaddr, 0x1E);
3572
+                ephy_data = rtl8168_ephy_read(tp, 0x1E);
3573
                 ephy_data |= (BIT_0);
3574
-                rtl8168_ephy_write(ioaddr, 0x1E, ephy_data);
3575
+                rtl8168_ephy_write(tp, 0x1E, ephy_data);
3576
 
3577
-                ephy_data = rtl8168_ephy_read(ioaddr, 0x19);
3578
+                ephy_data = rtl8168_ephy_read(tp, 0x19);
3579
                 ephy_data &= ~(BIT_15);
3580
-                rtl8168_ephy_write(ioaddr, 0x19, ephy_data);
3581
+                rtl8168_ephy_write(tp, 0x19, ephy_data);
3582
 
3583
                 break;
3584
         case CFG_METHOD_25:
3585
-                ephy_data = rtl8168_ephy_read(ioaddr, 0x00);
3586
+                ephy_data = rtl8168_ephy_read(tp, 0x00);
3587
                 ephy_data &= ~BIT_3;
3588
-                rtl8168_ephy_write(ioaddr, 0x00, ephy_data);
3589
-                ephy_data = rtl8168_ephy_read(ioaddr, 0x0C);
3590
+                rtl8168_ephy_write(tp, 0x00, ephy_data);
3591
+                ephy_data = rtl8168_ephy_read(tp, 0x0C);
3592
                 ephy_data &= ~(BIT_13 | BIT_12 | BIT_11 | BIT_10| BIT_9 | BIT_8 | BIT_7 | BIT_6 | BIT_5 | BIT_4);
3593
                 ephy_data |= (BIT_5 | BIT_11);
3594
-                rtl8168_ephy_write(ioaddr, 0x0C, ephy_data);
3595
+                rtl8168_ephy_write(tp, 0x0C, ephy_data);
3596
 
3597
-                rtl8168_ephy_write(ioaddr, 0x19, 0x7C00);
3598
-                rtl8168_ephy_write(ioaddr, 0x1E, 0x20EB);
3599
-                rtl8168_ephy_write(ioaddr, 0x0D, 0x1666);
3600
-                rtl8168_ephy_write(ioaddr, 0x00, 0x10A3);
3601
-                rtl8168_ephy_write(ioaddr, 0x06, 0xF050);
3602
+                rtl8168_ephy_write(tp, 0x19, 0x7C00);
3603
+                rtl8168_ephy_write(tp, 0x1E, 0x20EB);
3604
+                rtl8168_ephy_write(tp, 0x0D, 0x1666);
3605
+                rtl8168_ephy_write(tp, 0x00, 0x10A3);
3606
+                rtl8168_ephy_write(tp, 0x06, 0xF050);
3607
 
3608
                 SetPCIePhyBit(tp, 0x04, BIT_4);
3609
                 ClearPCIePhyBit(tp, 0x1D, BIT_14);
3610
@@ -9662,31 +9692,28 @@
3611
 
3612
                 break;
3613
         case CFG_METHOD_23:
3614
-                rtl8168_ephy_write(ioaddr, 0x00, 0x10AB);
3615
-                rtl8168_ephy_write(ioaddr, 0x06, 0xf030);
3616
-                rtl8168_ephy_write(ioaddr, 0x08, 0x2006);
3617
-                rtl8168_ephy_write(ioaddr, 0x0D, 0x1666);
3618
+                rtl8168_ephy_write(tp, 0x00, 0x10AB);
3619
+                rtl8168_ephy_write(tp, 0x06, 0xf030);
3620
+                rtl8168_ephy_write(tp, 0x08, 0x2006);
3621
+                rtl8168_ephy_write(tp, 0x0D, 0x1666);
3622
 
3623
-                ephy_data = rtl8168_ephy_read(ioaddr, 0x0C);
3624
+                ephy_data = rtl8168_ephy_read(tp, 0x0C);
3625
                 ephy_data &= ~(BIT_13 | BIT_12 | BIT_11 | BIT_10 | BIT_9 | BIT_8 | BIT_7 | BIT_6 | BIT_5 | BIT_4);
3626
-                rtl8168_ephy_write(ioaddr, 0x0C, ephy_data);
3627
+                rtl8168_ephy_write(tp, 0x0C, ephy_data);
3628
 
3629
                 break;
3630
         case CFG_METHOD_27:
3631
-                rtl8168_ephy_write(ioaddr, 0x00, 0x10A3);
3632
-                rtl8168_ephy_write(ioaddr, 0x19, 0xFC00);
3633
-                rtl8168_ephy_write(ioaddr, 0x1E, 0x20EA);
3634
+                rtl8168_ephy_write(tp, 0x00, 0x10A3);
3635
+                rtl8168_ephy_write(tp, 0x19, 0xFC00);
3636
+                rtl8168_ephy_write(tp, 0x1E, 0x20EA);
3637
 
3638
                 break;
3639
         case CFG_METHOD_28:
3640
-                SetPCIePhyBit(tp, 0x00, BIT_7);
3641
-                ClearAndSetPCIePhyBit(tp,
3642
-                                      0x0D,
3643
-                                      BIT_8,
3644
-                                      BIT_9
3645
-                                     );
3646
-                ClearPCIePhyBit(tp, 0x19, (BIT_15 | BIT_5 | BIT_0));
3647
-                SetPCIePhyBit(tp, 0x1E, BIT_13);
3648
+                rtl8168_ephy_write(tp, 0x00, 0x10A3);
3649
+                rtl8168_ephy_write(tp, 0x19, 0x7C00);
3650
+                rtl8168_ephy_write(tp, 0x1E, 0x20EB);
3651
+                rtl8168_ephy_write(tp, 0x0D, 0x1666);
3652
+                ClearPCIePhyBit(tp, 0x0B, BIT_0);
3653
 
3654
                 break;
3655
         case CFG_METHOD_29:
3656
@@ -9696,15 +9723,16 @@
3657
                 SetPCIePhyBit(tp, 0x1E, BIT_0);
3658
                 SetPCIePhyBit(tp, 0x1D, BIT_11);
3659
 
3660
-                rtl8168_ephy_write(ioaddr, 0x05, 0x2089);
3661
-                rtl8168_ephy_write(ioaddr, 0x06, 0x5881);
3662
+                rtl8168_ephy_write(tp, 0x05, 0x2089);
3663
+                rtl8168_ephy_write(tp, 0x06, 0x5881);
3664
 
3665
-                rtl8168_ephy_write(ioaddr, 0x04, 0x854A);
3666
-                rtl8168_ephy_write(ioaddr, 0x01, 0x068B);
3667
+                rtl8168_ephy_write(tp, 0x04, 0x854A);
3668
+                rtl8168_ephy_write(tp, 0x01, 0x068B);
3669
 
3670
                 break;
3671
         case CFG_METHOD_31:
3672
         case CFG_METHOD_32:
3673
+        case CFG_METHOD_33:
3674
                 ClearAndSetPCIePhyBit(tp,
3675
                                       0x19,
3676
                                       BIT_6,
3677
@@ -9716,6 +9744,10 @@
3678
                                       (BIT_12| BIT_8)
3679
                                      );
3680
 
3681
+                ClearPCIePhyBit(tp, 0x0C, BIT_4);
3682
+                ClearPCIePhyBit(tp, 0x4C, BIT_4);
3683
+                ClearPCIePhyBit(tp, 0x0B, BIT_0);
3684
+
3685
                 break;
3686
         }
3687
 }
3688
@@ -9728,7 +9760,7 @@
3689
         int retval = TRUE;
3690
 
3691
         switch (tp->mcfg) {
3692
-        case CFG_METHOD_21 ... CFG_METHOD_32:
3693
+        case CFG_METHOD_21 ... CFG_METHOD_33:
3694
                 rtl8168_mdio_write(tp,0x1f, 0x0B82);
3695
                 rtl8168_set_eth_phy_bit(tp, 0x10, BIT_4);
3696
 
3697
@@ -9760,7 +9792,7 @@
3698
         int retval = TRUE;
3699
 
3700
         switch (tp->mcfg) {
3701
-        case CFG_METHOD_21 ... CFG_METHOD_32:
3702
+        case CFG_METHOD_21 ... CFG_METHOD_33:
3703
                 rtl8168_mdio_write(tp, 0x1f, 0x0B82);
3704
                 rtl8168_clear_eth_phy_bit(tp, 0x10, BIT_4);
3705
 
3706
@@ -9820,6 +9852,7 @@
3707
         case CFG_METHOD_30:
3708
         case CFG_METHOD_31:
3709
         case CFG_METHOD_32:
3710
+        case CFG_METHOD_33:
3711
                 rtl8168_mdio_write(tp, 0x1F, 0x0A43);
3712
                 rtl8168_mdio_write(tp, 0x13, 0x801E);
3713
                 tp->hw_ram_code_ver = rtl8168_mdio_read(tp, 0x14);
3714
@@ -9875,6 +9908,7 @@
3715
         case CFG_METHOD_30:
3716
         case CFG_METHOD_31:
3717
         case CFG_METHOD_32:
3718
+        case CFG_METHOD_33:
3719
                 rtl8168_mdio_write(tp, 0x1F, 0x0A43);
3720
                 rtl8168_mdio_write(tp, 0x13, 0x801E);
3721
                 rtl8168_mdio_write(tp, 0x14, tp->sw_ram_code_ver);
3722
@@ -23515,7 +23549,8 @@
3723
                                 rtl8168_mdio_write(tp, 0x1F, 0x0000);
3724
                         }
3725
                 }
3726
-        } else if (tp->mcfg == CFG_METHOD_31 || tp->mcfg == CFG_METHOD_32) {
3727
+        } else if (tp->mcfg == CFG_METHOD_31 || tp->mcfg == CFG_METHOD_32 ||
3728
+                   tp->mcfg == CFG_METHOD_33) {
3729
                 rtl8168_mdio_write(tp, 0x1F, 0x0A43);
3730
                 rtl8168_mdio_write(tp, 0x13, 0x808E);
3731
                 ClearAndSetEthPhyBit( tp,
3732
@@ -23691,7 +23726,8 @@
3733
                 rtl8168_mdio_write(tp, 0x14, 0x1065);
3734
                 rtl8168_mdio_write(tp, 0x1F, 0x0000);
3735
         } else if (tp->mcfg == CFG_METHOD_29 || tp->mcfg == CFG_METHOD_30 ||
3736
-                   tp->mcfg == CFG_METHOD_31 || tp->mcfg == CFG_METHOD_32) {
3737
+                   tp->mcfg == CFG_METHOD_31 || tp->mcfg == CFG_METHOD_32 ||
3738
+                   tp->mcfg == CFG_METHOD_33) {
3739
                 //enable EthPhyPPSW
3740
                 rtl8168_mdio_write(tp, 0x1F, 0x0A44);
3741
                 rtl8168_set_eth_phy_bit( tp, 0x11, BIT_7 );
3742
@@ -23702,7 +23738,8 @@
3743
         if (tp->mcfg == CFG_METHOD_25 || tp->mcfg == CFG_METHOD_26 ||
3744
             tp->mcfg == CFG_METHOD_27 || tp->mcfg == CFG_METHOD_28 ||
3745
             tp->mcfg == CFG_METHOD_29 || tp->mcfg == CFG_METHOD_30 ||
3746
-            tp->mcfg == CFG_METHOD_31 || tp->mcfg == CFG_METHOD_32) {
3747
+            tp->mcfg == CFG_METHOD_31 || tp->mcfg == CFG_METHOD_32 ||
3748
+            tp->mcfg == CFG_METHOD_33) {
3749
                 if (aspm)
3750
                         rtl8168_enable_ocp_phy_power_saving(dev);
3751
         }
3752
@@ -23778,7 +23815,6 @@
3753
 rtl8168_get_bios_setting(struct net_device *dev)
3754
 {
3755
         struct rtl8168_private *tp = netdev_priv(dev);
3756
-        void __iomem *ioaddr = tp->mmio_addr;
3757
 
3758
         switch (tp->mcfg) {
3759
         case CFG_METHOD_9:
3760
@@ -23805,7 +23841,8 @@
3761
         case CFG_METHOD_30:
3762
         case CFG_METHOD_31:
3763
         case CFG_METHOD_32:
3764
-                tp->bios_setting = RTL_R32(0x8c);
3765
+        case CFG_METHOD_33:
3766
+                tp->bios_setting = RTL_R32(tp, 0x8c);
3767
                 break;
3768
         }
3769
 }
3770
@@ -23814,7 +23851,6 @@
3771
 rtl8168_set_bios_setting(struct net_device *dev)
3772
 {
3773
         struct rtl8168_private *tp = netdev_priv(dev);
3774
-        void __iomem *ioaddr = tp->mmio_addr;
3775
 
3776
         switch (tp->mcfg) {
3777
         case CFG_METHOD_9:
3778
@@ -23841,7 +23877,8 @@
3779
         case CFG_METHOD_30:
3780
         case CFG_METHOD_31:
3781
         case CFG_METHOD_32:
3782
-                RTL_W32(0x8C, tp->bios_setting);
3783
+        case CFG_METHOD_33:
3784
+                RTL_W32(tp, 0x8C, tp->bios_setting);
3785
                 break;
3786
         }
3787
 }
3788
@@ -23851,7 +23888,6 @@
3789
 {
3790
         struct rtl8168_private *tp = netdev_priv(dev);
3791
         struct pci_dev *pdev = tp->pci_dev;
3792
-        void __iomem *ioaddr = tp->mmio_addr;
3793
 
3794
         rtl8168_get_bios_setting(dev);
3795
 
3796
@@ -23868,6 +23904,7 @@
3797
                 break;
3798
         case CFG_METHOD_31:
3799
         case CFG_METHOD_32:
3800
+        case CFG_METHOD_33:
3801
                 tp->HwSuppDashVer = 3;
3802
                 break;
3803
         default:
3804
@@ -23878,6 +23915,7 @@
3805
         switch (tp->mcfg) {
3806
         case CFG_METHOD_31:
3807
         case CFG_METHOD_32:
3808
+        case CFG_METHOD_33:
3809
                 tp->HwPkgDet = rtl8168_mac_ocp_read(tp, 0xDC00);
3810
                 tp->HwPkgDet = (tp->HwPkgDet >> 3) & 0x0F;
3811
                 break;
3812
@@ -23899,13 +23937,33 @@
3813
         case CFG_METHOD_30:
3814
         case CFG_METHOD_31:
3815
         case CFG_METHOD_32:
3816
+        case CFG_METHOD_33:
3817
                 tp->HwSuppNowIsOobVer = 1;
3818
                 break;
3819
         }
3820
 
3821
         switch (tp->mcfg) {
3822
+        case CFG_METHOD_21:
3823
+        case CFG_METHOD_22:
3824
+        case CFG_METHOD_23:
3825
+        case CFG_METHOD_24:
3826
+        case CFG_METHOD_25:
3827
+        case CFG_METHOD_26:
3828
+        case CFG_METHOD_27:
3829
+        case CFG_METHOD_28:
3830
+        case CFG_METHOD_29:
3831
+        case CFG_METHOD_30:
3832
+        case CFG_METHOD_31:
3833
+        case CFG_METHOD_32:
3834
+        case CFG_METHOD_33:
3835
+                tp->HwSuppPhyOcpVer = 1;
3836
+                break;
3837
+        }
3838
+
3839
+        switch (tp->mcfg) {
3840
         case CFG_METHOD_31:
3841
         case CFG_METHOD_32:
3842
+        case CFG_METHOD_33:
3843
                 tp->HwPcieSNOffset = 0x16C;
3844
                 break;
3845
         case CFG_METHOD_DEFAULT:
3846
@@ -23929,26 +23987,21 @@
3847
                 if (HW_DASH_SUPPORT_TYPE_3(tp)) {
3848
                         u64 CmacMemPhysAddress;
3849
                         void __iomem *cmac_ioaddr = NULL;
3850
+                        struct pci_dev *pdev_cmac;
3851
+
3852
+                        pdev_cmac = pci_get_slot(pdev->bus, PCI_DEVFN(PCI_SLOT(pdev->devfn), 0));
3853
 
3854
                         //map CMAC IO space
3855
-                        CmacMemPhysAddress = rtl8168_csi_other_fun_read(tp, 0, 0x18);
3856
-                        if (!(CmacMemPhysAddress & BIT_0)) {
3857
-                                if (CmacMemPhysAddress & BIT_2)
3858
-                                        CmacMemPhysAddress |=  (u64)rtl8168_csi_other_fun_read(tp, 0, 0x1C) << 32;
3859
-
3860
-                                CmacMemPhysAddress &=  0xFFFFFFF0;
3861
-                                /* ioremap MMIO region */
3862
-                                cmac_ioaddr = ioremap(CmacMemPhysAddress, R8168_REGS_SIZE);
3863
-                        }
3864
+                        CmacMemPhysAddress = pci_resource_start(pdev_cmac, 2);
3865
+
3866
+                        /* ioremap MMIO region */
3867
+                        cmac_ioaddr = ioremap(CmacMemPhysAddress, R8168_REGS_SIZE);
3868
 
3869
                         if (cmac_ioaddr == NULL) {
3870
 #if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0)
3871
                                 if (netif_msg_probe(tp))
3872
                                         dev_err(&pdev->dev, "cannot remap CMAC MMIO, aborting\n");
3873
 #endif //LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0)
3874
-                        }
3875
-
3876
-                        if (cmac_ioaddr == NULL) {
3877
                                 tp->DASH = 0;
3878
                         } else {
3879
                                 tp->mapped_cmac_ioaddr = cmac_ioaddr;
3880
@@ -24014,6 +24067,7 @@
3881
                 case CFG_METHOD_30:
3882
                 case CFG_METHOD_31:
3883
                 case CFG_METHOD_32:
3884
+                case CFG_METHOD_33:
3885
                         tp->org_pci_offset_99 = rtl8168_csi_fun0_read_byte(tp, 0x99);
3886
                         tp->org_pci_offset_99 &= ~(BIT_5|BIT_6);
3887
                         break;
3888
@@ -24030,6 +24084,7 @@
3889
                         break;
3890
                 case CFG_METHOD_31:
3891
                 case CFG_METHOD_32:
3892
+                case CFG_METHOD_33:
3893
                         tp->org_pci_offset_180 = rtl8168_csi_fun0_read_byte(tp, 0x214);
3894
                         break;
3895
                 }
3896
@@ -24111,7 +24166,8 @@
3897
         case CFG_METHOD_29:
3898
         case CFG_METHOD_30:
3899
         case CFG_METHOD_31:
3900
-        case CFG_METHOD_32: {
3901
+        case CFG_METHOD_32:
3902
+        case CFG_METHOD_33: {
3903
                 u16 rg_saw_cnt;
3904
 
3905
                 rtl8168_mdio_write(tp, 0x1F, 0x0C42);
3906
@@ -24199,6 +24255,7 @@
3907
         case CFG_METHOD_30:
3908
         case CFG_METHOD_31:
3909
         case CFG_METHOD_32:
3910
+        case CFG_METHOD_33:
3911
                 tp->HwSuppMagicPktVer = WAKEUP_MAGIC_PACKET_V2;
3912
                 break;
3913
         case CFG_METHOD_DEFAULT:
3914
@@ -24230,6 +24287,7 @@
3915
         case CFG_METHOD_28:
3916
         case CFG_METHOD_31:
3917
         case CFG_METHOD_32:
3918
+        case CFG_METHOD_33:
3919
                 tp->HwSuppCheckPhyDisableModeVer = 3;
3920
                 break;
3921
         }
3922
@@ -24247,6 +24305,7 @@
3923
         case CFG_METHOD_30:
3924
         case CFG_METHOD_31:
3925
         case CFG_METHOD_32:
3926
+        case CFG_METHOD_33:
3927
                 tp->HwSuppGigaForceMode = TRUE;
3928
                 break;
3929
         }
3930
@@ -24291,6 +24350,7 @@
3931
                 break;
3932
         case CFG_METHOD_31:
3933
         case CFG_METHOD_32:
3934
+        case CFG_METHOD_33:
3935
                 tp->sw_ram_code_ver = NIC_RAMCODE_VERSION_CFG_METHOD_31;
3936
                 break;
3937
         }
3938
@@ -24300,7 +24360,7 @@
3939
                 tp->NotWrMcuPatchCode = TRUE;
3940
         }
3941
 
3942
-        tp->NicCustLedValue = RTL_R16(CustomLED);
3943
+        tp->NicCustLedValue = RTL_R16(tp, CustomLED);
3944
 
3945
         rtl8168_get_hw_wol(dev);
3946
 
3947
@@ -24323,10 +24383,10 @@
3948
 
3949
 static void
3950
 rtl8168_release_board(struct pci_dev *pdev,
3951
-                      struct net_device *dev,
3952
-                      void __iomem *ioaddr)
3953
+                      struct net_device *dev)
3954
 {
3955
         struct rtl8168_private *tp = netdev_priv(dev);
3956
+        void __iomem *ioaddr = tp->mmio_addr;
3957
 
3958
         rtl8168_set_bios_setting(dev);
3959
         rtl8168_rar_set(tp, tp->org_mac_addr);
3960
@@ -24353,12 +24413,11 @@
3961
 rtl8168_get_mac_address(struct net_device *dev)
3962
 {
3963
         struct rtl8168_private *tp = netdev_priv(dev);
3964
-        void __iomem *ioaddr = tp->mmio_addr;
3965
         int i;
3966
         u8 mac_addr[MAC_ADDR_LEN];
3967
 
3968
         for (i = 0; i < MAC_ADDR_LEN; i++)
3969
-                mac_addr[i] = RTL_R8(MAC0 + i);
3970
+                mac_addr[i] = RTL_R8(tp, MAC0 + i);
3971
 
3972
         if (tp->mcfg == CFG_METHOD_18 ||
3973
             tp->mcfg == CFG_METHOD_19 ||
3974
@@ -24374,9 +24433,10 @@
3975
             tp->mcfg == CFG_METHOD_29 ||
3976
             tp->mcfg == CFG_METHOD_30 ||
3977
             tp->mcfg == CFG_METHOD_31 ||
3978
-            tp->mcfg == CFG_METHOD_32) {
3979
-                *(u32*)&mac_addr[0] = rtl8168_eri_read(ioaddr, 0xE0, 4, ERIAR_ExGMAC);
3980
-                *(u16*)&mac_addr[4] = rtl8168_eri_read(ioaddr, 0xE4, 2, ERIAR_ExGMAC);
3981
+            tp->mcfg == CFG_METHOD_32 ||
3982
+            tp->mcfg == CFG_METHOD_33) {
3983
+                *(u32*)&mac_addr[0] = rtl8168_eri_read(tp, 0xE0, 4, ERIAR_ExGMAC);
3984
+                *(u16*)&mac_addr[4] = rtl8168_eri_read(tp, 0xE4, 2, ERIAR_ExGMAC);
3985
         } else {
3986
                 if (tp->eeprom_type != EEPROM_TYPE_NONE) {
3987
                         u16 *pUshort = (u16*)mac_addr;
3988
@@ -24397,7 +24457,8 @@
3989
                             tp->mcfg == CFG_METHOD_29 ||
3990
                             tp->mcfg == CFG_METHOD_30 ||
3991
                             tp->mcfg == CFG_METHOD_31 ||
3992
-                            tp->mcfg == CFG_METHOD_32) {
3993
+                            tp->mcfg == CFG_METHOD_32 ||
3994
+                            tp->mcfg == CFG_METHOD_33) {
3995
                                 *pUshort++ = rtl8168_eeprom_read_sc(tp, 1);
3996
                                 *pUshort++ = rtl8168_eeprom_read_sc(tp, 2);
3997
                                 *pUshort = rtl8168_eeprom_read_sc(tp, 3);
3998
@@ -24422,7 +24483,7 @@
3999
         rtl8168_rar_set(tp, mac_addr);
4000
 
4001
         for (i = 0; i < MAC_ADDR_LEN; i++) {
4002
-                dev->dev_addr[i] = RTL_R8(MAC0 + i);
4003
+                dev->dev_addr[i] = RTL_R8(tp, MAC0 + i);
4004
                 tp->org_mac_addr[i] = dev->dev_addr[i]; /* keep the original MAC address */
4005
         }
4006
 #if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,13)
4007
@@ -24472,7 +24533,6 @@
4008
 rtl8168_rar_set(struct rtl8168_private *tp,
4009
                 uint8_t *addr)
4010
 {
4011
-        void __iomem *ioaddr = tp->mmio_addr;
4012
         uint32_t rar_low = 0;
4013
         uint32_t rar_high = 0;
4014
 
4015
@@ -24485,20 +24545,20 @@
4016
                     ((uint32_t) addr[5] << 8));
4017
 
4018
         rtl8168_enable_cfg9346_write(tp);
4019
-        RTL_W32(MAC0, rar_low);
4020
-        RTL_W32(MAC4, rar_high);
4021
+        RTL_W32(tp, MAC0, rar_low);
4022
+        RTL_W32(tp, MAC4, rar_high);
4023
 
4024
         switch (tp->mcfg) {
4025
         case CFG_METHOD_14:
4026
         case CFG_METHOD_15:
4027
-                RTL_W32(SecMAC0, rar_low);
4028
-                RTL_W16(SecMAC4, (uint16_t)rar_high);
4029
+                RTL_W32(tp, SecMAC0, rar_low);
4030
+                RTL_W16(tp, SecMAC4, (uint16_t)rar_high);
4031
                 break;
4032
         }
4033
 
4034
         if (tp->mcfg == CFG_METHOD_17) {
4035
-                rtl8168_eri_write(ioaddr, 0xf0, 4, rar_low << 16, ERIAR_ExGMAC);
4036
-                rtl8168_eri_write(ioaddr, 0xf4, 4, rar_low >> 16 | rar_high << 16, ERIAR_ExGMAC);
4037
+                rtl8168_eri_write(tp, 0xf0, 4, rar_low << 16, ERIAR_ExGMAC);
4038
+                rtl8168_eri_write(tp, 0xf4, 4, rar_low >> 16 | rar_high << 16, ERIAR_ExGMAC);
4039
         }
4040
 
4041
         rtl8168_disable_cfg9346_write(tp);
4042
@@ -25291,6 +25351,7 @@
4043
         case CFG_METHOD_30:
4044
         case CFG_METHOD_31:
4045
         case CFG_METHOD_32:
4046
+        case CFG_METHOD_33:
4047
                 rtl8168_wait_phy_ups_resume(dev, 3);
4048
                 break;
4049
         };
4050
@@ -25300,7 +25361,6 @@
4051
 rtl8168_phy_power_down(struct net_device *dev)
4052
 {
4053
         struct rtl8168_private *tp = netdev_priv(dev);
4054
-        void __iomem *ioaddr = tp->mmio_addr;
4055
         u32 csi_tmp;
4056
 
4057
         switch (tp->mcfg) {
4058
@@ -25308,9 +25368,9 @@
4059
         case CFG_METHOD_22:
4060
         case CFG_METHOD_23:
4061
         case CFG_METHOD_24:
4062
-                csi_tmp = rtl8168_eri_read(ioaddr, 0x1AB, 1, ERIAR_ExGMAC);
4063
+                csi_tmp = rtl8168_eri_read(tp, 0x1AB, 1, ERIAR_ExGMAC);
4064
                 csi_tmp &= ~( BIT_2 | BIT_3 | BIT_4 | BIT_5 | BIT_6 | BIT_7 );
4065
-                rtl8168_eri_write(ioaddr, 0x1AB, 1, csi_tmp, ERIAR_ExGMAC);
4066
+                rtl8168_eri_write(tp, 0x1AB, 1, csi_tmp, ERIAR_ExGMAC);
4067
                 break;
4068
         }
4069
 
4070
@@ -25474,8 +25534,10 @@
4071
                 goto err_out_free_res;
4072
         }
4073
 
4074
+        tp->mmio_addr = ioaddr;
4075
+
4076
         /* Identify chip attached to board */
4077
-        rtl8168_get_mac_version(tp, ioaddr);
4078
+        rtl8168_get_mac_version(tp);
4079
 
4080
         rtl8168_print_mac_version(tp);
4081
 
4082
@@ -25806,7 +25868,6 @@
4083
         tp = netdev_priv(dev);
4084
         assert(ioaddr != NULL);
4085
 
4086
-        tp->mmio_addr = ioaddr;
4087
         tp->set_speed = rtl8168_set_speed_xmii;
4088
         tp->get_settings = rtl8168_gset_xmii;
4089
         tp->phy_reset_enable = rtl8168_xmii_reset_enable;
4090
@@ -25838,7 +25899,7 @@
4091
         }
4092
 #endif
4093
 
4094
-        tp->cp_cmd |= RTL_R16(CPlusCmd);
4095
+        tp->cp_cmd |= RTL_R16(tp, CPlusCmd);
4096
         if (tp->mcfg != CFG_METHOD_DEFAULT) {
4097
                 dev->features |= NETIF_F_IP_CSUM;
4098
 #if LINUX_VERSION_CODE < KERNEL_VERSION(3,0,0)
4099
@@ -25915,7 +25976,7 @@
4100
                 rtl8168_eeprom_type(tp);
4101
 
4102
         if (tp->eeprom_type == EEPROM_TYPE_93C46 || tp->eeprom_type == EEPROM_TYPE_93C56)
4103
-                rtl8168_set_eeprom_sel_low(ioaddr);
4104
+                rtl8168_set_eeprom_sel_low(tp);
4105
 
4106
         rtl8168_get_mac_address(dev);
4107
 
4108
@@ -25925,7 +25986,8 @@
4109
         init_completion(&tp->fw_req);
4110
 #endif
4111
 
4112
-        tp->tally_vaddr = pci_alloc_consistent(pdev, sizeof(*tp->tally_vaddr), &tp->tally_paddr);
4113
+        tp->tally_vaddr = dma_alloc_coherent(&pdev->dev, sizeof(*tp->tally_vaddr),
4114
+                                             &tp->tally_paddr, GFP_KERNEL);
4115
         if (!tp->tally_vaddr) {
4116
                 rc = -ENOMEM;
4117
                 goto err_out;
4118
@@ -25954,8 +26016,8 @@
4119
 
4120
 err_out:
4121
         if (tp->tally_vaddr != NULL) {
4122
-                pci_free_consistent(pdev, sizeof(*tp->tally_vaddr), tp->tally_vaddr,
4123
-                                    tp->tally_paddr);
4124
+                dma_free_coherent(&pdev->dev, sizeof(*tp->tally_vaddr), tp->tally_vaddr,
4125
+                                  tp->tally_paddr);
4126
 
4127
                 tp->tally_vaddr = NULL;
4128
         }
4129
@@ -25963,7 +26025,7 @@
4130
         RTL_NAPI_DEL(tp);
4131
 #endif
4132
         rtl8168_disable_msi(pdev, tp);
4133
-        rtl8168_release_board(pdev, dev, ioaddr);
4134
+        rtl8168_release_board(pdev, dev);
4135
 
4136
         goto out;
4137
 }
4138
@@ -25980,7 +26042,7 @@
4139
 #ifdef  CONFIG_R8168_NAPI
4140
         RTL_NAPI_DEL(tp);
4141
 #endif
4142
-        if (tp->DASH)
4143
+        if (HW_DASH_SUPPORT_DASH(tp))
4144
                 rtl8168_driver_stop(tp);
4145
 
4146
         unregister_netdev(dev);
4147
@@ -25989,11 +26051,11 @@
4148
         rtl8168_proc_remove(dev);
4149
 #endif
4150
         if (tp->tally_vaddr != NULL) {
4151
-                pci_free_consistent(pdev, sizeof(*tp->tally_vaddr), tp->tally_vaddr, tp->tally_paddr);
4152
+                dma_free_coherent(&pdev->dev, sizeof(*tp->tally_vaddr), tp->tally_vaddr, tp->tally_paddr);
4153
                 tp->tally_vaddr = NULL;
4154
         }
4155
 
4156
-        rtl8168_release_board(pdev, dev, tp->mmio_addr);
4157
+        rtl8168_release_board(pdev, dev);
4158
         pci_set_drvdata(pdev, NULL);
4159
 }
4160
 
4161
@@ -26023,19 +26085,19 @@
4162
          * Rx and Tx descriptors needs 256 bytes alignment.
4163
          * pci_alloc_consistent provides more.
4164
          */
4165
-        tp->TxDescArray = pci_alloc_consistent(pdev, R8168_TX_RING_BYTES,
4166
-                                               &tp->TxPhyAddr);
4167
+        tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8168_TX_RING_BYTES,
4168
+                                             &tp->TxPhyAddr, GFP_KERNEL);
4169
         if (!tp->TxDescArray)
4170
                 goto err_free_all_allocated_mem;
4171
 
4172
-        tp->RxDescArray = pci_alloc_consistent(pdev, R8168_RX_RING_BYTES,
4173
-                                               &tp->RxPhyAddr);
4174
+        tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8168_RX_RING_BYTES,
4175
+                                             &tp->RxPhyAddr, GFP_KERNEL);
4176
         if (!tp->RxDescArray)
4177
                 goto err_free_all_allocated_mem;
4178
 
4179
         if (tp->UseSwPaddingShortPkt) {
4180
-                tp->ShortPacketEmptyBuffer = pci_alloc_consistent(pdev, SHORT_PACKET_PADDING_BUF_SIZE,
4181
-                                             &tp->ShortPacketEmptyBufferPhy);
4182
+                tp->ShortPacketEmptyBuffer = dma_alloc_coherent(&pdev->dev, SHORT_PACKET_PADDING_BUF_SIZE,
4183
+                                             &tp->ShortPacketEmptyBufferPhy, GFP_KERNEL);
4184
                 if (!tp->ShortPacketEmptyBuffer)
4185
                         goto err_free_all_allocated_mem;
4186
 
4187
@@ -26105,20 +26167,20 @@
4188
 
4189
 err_free_all_allocated_mem:
4190
         if (tp->RxDescArray != NULL) {
4191
-                pci_free_consistent(pdev, R8168_RX_RING_BYTES, tp->RxDescArray,
4192
-                                    tp->RxPhyAddr);
4193
+                dma_free_coherent(&pdev->dev, R8168_RX_RING_BYTES, tp->RxDescArray,
4194
+                                  tp->RxPhyAddr);
4195
                 tp->RxDescArray = NULL;
4196
         }
4197
 
4198
         if (tp->TxDescArray != NULL) {
4199
-                pci_free_consistent(pdev, R8168_TX_RING_BYTES, tp->TxDescArray,
4200
-                                    tp->TxPhyAddr);
4201
+                dma_free_coherent(&pdev->dev, R8168_TX_RING_BYTES, tp->TxDescArray,
4202
+                                  tp->TxPhyAddr);
4203
                 tp->TxDescArray = NULL;
4204
         }
4205
 
4206
         if (tp->ShortPacketEmptyBuffer != NULL) {
4207
-                pci_free_consistent(pdev, ETH_ZLEN, tp->ShortPacketEmptyBuffer,
4208
-                                    tp->ShortPacketEmptyBufferPhy);
4209
+                dma_free_coherent(&pdev->dev, ETH_ZLEN, tp->ShortPacketEmptyBuffer,
4210
+                                  tp->ShortPacketEmptyBufferPhy);
4211
                 tp->ShortPacketEmptyBuffer = NULL;
4212
         }
4213
 
4214
@@ -26129,31 +26191,30 @@
4215
 rtl8168_dsm(struct net_device *dev, int dev_state)
4216
 {
4217
         struct rtl8168_private *tp = netdev_priv(dev);
4218
-        void __iomem *ioaddr = tp->mmio_addr;
4219
 
4220
         switch (dev_state) {
4221
         case DSM_MAC_INIT:
4222
                 if ((tp->mcfg == CFG_METHOD_5) || (tp->mcfg == CFG_METHOD_6)) {
4223
-                        if (RTL_R8(MACDBG) & 0x80)
4224
-                                RTL_W8(GPIO, RTL_R8(GPIO) | GPIO_en);
4225
+                        if (RTL_R8(tp, MACDBG) & 0x80)
4226
+                                RTL_W8(tp, GPIO, RTL_R8(tp, GPIO) | GPIO_en);
4227
                         else
4228
-                                RTL_W8(GPIO, RTL_R8(GPIO) & ~GPIO_en);
4229
+                                RTL_W8(tp, GPIO, RTL_R8(tp, GPIO) & ~GPIO_en);
4230
                 }
4231
 
4232
                 break;
4233
         case DSM_NIC_GOTO_D3:
4234
         case DSM_IF_DOWN:
4235
                 if ((tp->mcfg == CFG_METHOD_5) || (tp->mcfg == CFG_METHOD_6)) {
4236
-                        if (RTL_R8(MACDBG) & 0x80)
4237
-                                RTL_W8(GPIO, RTL_R8(GPIO) & ~GPIO_en);
4238
+                        if (RTL_R8(tp, MACDBG) & 0x80)
4239
+                                RTL_W8(tp, GPIO, RTL_R8(tp, GPIO) & ~GPIO_en);
4240
                 }
4241
                 break;
4242
 
4243
         case DSM_NIC_RESUME_D3:
4244
         case DSM_IF_UP:
4245
                 if ((tp->mcfg == CFG_METHOD_5) || (tp->mcfg == CFG_METHOD_6)) {
4246
-                        if (RTL_R8(MACDBG) & 0x80)
4247
-                                RTL_W8(GPIO, RTL_R8(GPIO) | GPIO_en);
4248
+                        if (RTL_R8(tp, MACDBG) & 0x80)
4249
+                                RTL_W8(tp, GPIO, RTL_R8(tp, GPIO) | GPIO_en);
4250
                 }
4251
 
4252
                 break;
4253
@@ -26207,7 +26268,6 @@
4254
 rtl8168_hw_set_rx_packet_filter(struct net_device *dev)
4255
 {
4256
         struct rtl8168_private *tp = netdev_priv(dev);
4257
-        void __iomem *ioaddr = tp->mmio_addr;
4258
         u32 mc_filter[2];   /* Multicast hash filter */
4259
         int rx_mode;
4260
         u32 tmp = 0;
4261
@@ -26261,11 +26321,11 @@
4262
         mc_filter[1] = swab32(tmp);
4263
 
4264
         tp->rtl8168_rx_config = rtl_chip_info[tp->chipset].RCR_Cfg;
4265
-        tmp = tp->rtl8168_rx_config | rx_mode | (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
4266
+        tmp = tp->rtl8168_rx_config | rx_mode | (RTL_R32(tp, RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
4267
 
4268
-        RTL_W32(RxConfig, tmp);
4269
-        RTL_W32(MAR0 + 0, mc_filter[0]);
4270
-        RTL_W32(MAR0 + 4, mc_filter[1]);
4271
+        RTL_W32(tp, RxConfig, tmp);
4272
+        RTL_W32(tp, MAR0 + 0, mc_filter[0]);
4273
+        RTL_W32(tp, MAR0 + 4, mc_filter[1]);
4274
 }
4275
 
4276
 static void
4277
@@ -26285,7 +26345,6 @@
4278
 rtl8168_hw_config(struct net_device *dev)
4279
 {
4280
         struct rtl8168_private *tp = netdev_priv(dev);
4281
-        void __iomem *ioaddr = tp->mmio_addr;
4282
         struct pci_dev *pdev = tp->pci_dev;
4283
         u8 device_control;
4284
         u16 mac_ocp_data;
4285
@@ -26299,7 +26358,7 @@
4286
         }
4287
 #endif
4288
 
4289
-        RTL_W32(RxConfig, (RX_DMA_BURST << RxCfgDMAShift));
4290
+        RTL_W32(tp, RxConfig, (RX_DMA_BURST << RxCfgDMAShift));
4291
 
4292
         rtl8168_hw_reset(dev);
4293
 
4294
@@ -26324,9 +26383,10 @@
4295
         case CFG_METHOD_30:
4296
         case CFG_METHOD_31:
4297
         case CFG_METHOD_32:
4298
-                RTL_W8(0xF1, RTL_R8(0xF1) & ~BIT_7);
4299
-                RTL_W8(Config2, RTL_R8(Config2) & ~BIT_7);
4300
-                RTL_W8(Config5, RTL_R8(Config5) & ~BIT_0);
4301
+        case CFG_METHOD_33:
4302
+                RTL_W8(tp, 0xF1, RTL_R8(tp, 0xF1) & ~BIT_7);
4303
+                RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~BIT_7);
4304
+                RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~BIT_0);
4305
                 break;
4306
         }
4307
 
4308
@@ -26345,7 +26405,8 @@
4309
         case CFG_METHOD_30:
4310
         case CFG_METHOD_31:
4311
         case CFG_METHOD_32:
4312
-                RTL_W8(Config3, RTL_R8(Config3) & ~BIT_1);
4313
+        case CFG_METHOD_33:
4314
+                RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~BIT_1);
4315
                 break;
4316
         }
4317
 
4318
@@ -26368,13 +26429,14 @@
4319
         case CFG_METHOD_30:
4320
         case CFG_METHOD_31:
4321
         case CFG_METHOD_32:
4322
-                csi_tmp = rtl8168_eri_read(ioaddr, 0xDE, 1, ERIAR_ExGMAC);
4323
+        case CFG_METHOD_33:
4324
+                csi_tmp = rtl8168_eri_read(tp, 0xDE, 1, ERIAR_ExGMAC);
4325
                 csi_tmp &= ~BIT_0;
4326
-                rtl8168_eri_write(ioaddr, 0xDE, 1, csi_tmp, ERIAR_ExGMAC);
4327
+                rtl8168_eri_write(tp, 0xDE, 1, csi_tmp, ERIAR_ExGMAC);
4328
                 break;
4329
         }
4330
 
4331
-        RTL_W8(MTPS, Reserved1_data);
4332
+        RTL_W8(tp, MTPS, Reserved1_data);
4333
 
4334
         tp->cp_cmd |= INTT_1;
4335
         if (tp->use_timer_interrrupt)
4336
@@ -26382,7 +26444,7 @@
4337
         else
4338
                 tp->cp_cmd &= ~PktCntrDisable;
4339
 
4340
-        RTL_W16(IntrMitigate, 0x5f51);
4341
+        RTL_W16(tp, IntrMitigate, 0x5f51);
4342
 
4343
         rtl8168_tally_counter_addr_fill(tp);
4344
 
4345
@@ -26390,30 +26452,30 @@
4346
 
4347
         /* Set DMA burst size and Interframe Gap Time */
4348
         if (tp->mcfg == CFG_METHOD_1)
4349
-                RTL_W32(TxConfig, (TX_DMA_BURST_512 << TxDMAShift) |
4350
+                RTL_W32(tp, TxConfig, (TX_DMA_BURST_512 << TxDMAShift) |
4351
                         (InterFrameGap << TxInterFrameGapShift));
4352
         else
4353
-                RTL_W32(TxConfig, (TX_DMA_BURST_unlimited << TxDMAShift) |
4354
+                RTL_W32(tp, TxConfig, (TX_DMA_BURST_unlimited << TxDMAShift) |
4355
                         (InterFrameGap << TxInterFrameGapShift));
4356
 
4357
         if (tp->mcfg == CFG_METHOD_4) {
4358
                 set_offset70F(tp, 0x27);
4359
 
4360
-                RTL_W8(DBG_reg, (0x0E << 4) | Fix_Nak_1 | Fix_Nak_2);
4361
+                RTL_W8(tp, DBG_reg, (0x0E << 4) | Fix_Nak_1 | Fix_Nak_2);
4362
 
4363
-                RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4364
+                RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4365
 
4366
                 //disable clock request.
4367
                 pci_write_config_byte(pdev, 0x81, 0x00);
4368
 
4369
                 if (dev->mtu > ETH_DATA_LEN) {
4370
-                        RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4371
-                        RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
4372
+                        RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4373
+                        RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
4374
 
4375
                         set_offset79(tp, 0x20);
4376
                 } else {
4377
-                        RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4378
-                        RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
4379
+                        RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4380
+                        RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
4381
 
4382
                         set_offset79(tp, 0x50);
4383
                 }
4384
@@ -26432,19 +26494,19 @@
4385
 
4386
                 set_offset70F(tp, 0x27);
4387
 
4388
-                RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4389
+                RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4390
 
4391
                 //disable clock request.
4392
                 pci_write_config_byte(pdev, 0x81, 0x00);
4393
 
4394
                 if (dev->mtu > ETH_DATA_LEN) {
4395
-                        RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4396
-                        RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
4397
+                        RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4398
+                        RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
4399
 
4400
                         set_offset79(tp, 0x20);
4401
                 } else {
4402
-                        RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4403
-                        RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
4404
+                        RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4405
+                        RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
4406
 
4407
                         set_offset79(tp, 0x50);
4408
                 }
4409
@@ -26458,19 +26520,19 @@
4410
         } else if (tp->mcfg == CFG_METHOD_6) {
4411
                 set_offset70F(tp, 0x27);
4412
 
4413
-                RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4414
+                RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4415
 
4416
                 //disable clock request.
4417
                 pci_write_config_byte(pdev, 0x81, 0x00);
4418
 
4419
                 if (dev->mtu > ETH_DATA_LEN) {
4420
-                        RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4421
-                        RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
4422
+                        RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4423
+                        RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
4424
 
4425
                         set_offset79(tp, 0x20);
4426
                 } else {
4427
-                        RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4428
-                        RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
4429
+                        RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4430
+                        RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
4431
 
4432
                         set_offset79(tp, 0x50);
4433
                 }
4434
@@ -26484,21 +26546,21 @@
4435
         } else if (tp->mcfg == CFG_METHOD_7) {
4436
                 set_offset70F(tp, 0x27);
4437
 
4438
-                rtl8168_eri_write(ioaddr, 0x1EC, 1, 0x07, ERIAR_ASF);
4439
+                rtl8168_eri_write(tp, 0x1EC, 1, 0x07, ERIAR_ASF);
4440
 
4441
                 //disable clock request.
4442
                 pci_write_config_byte(pdev, 0x81, 0x00);
4443
 
4444
-                RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4445
+                RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4446
 
4447
                 if (dev->mtu > ETH_DATA_LEN) {
4448
-                        RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4449
-                        RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
4450
+                        RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4451
+                        RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
4452
 
4453
                         set_offset79(tp, 0x20);
4454
                 } else {
4455
-                        RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4456
-                        RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
4457
+                        RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4458
+                        RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
4459
 
4460
 
4461
                         set_offset79(tp, 0x50);
4462
@@ -26507,23 +26569,23 @@
4463
 
4464
                 set_offset70F(tp, 0x27);
4465
 
4466
-                rtl8168_eri_write(ioaddr, 0x1EC, 1, 0x07, ERIAR_ASF);
4467
+                rtl8168_eri_write(tp, 0x1EC, 1, 0x07, ERIAR_ASF);
4468
 
4469
                 //disable clock request.
4470
                 pci_write_config_byte(pdev, 0x81, 0x00);
4471
 
4472
-                RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4473
+                RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4474
 
4475
-                RTL_W8(0xD1, 0x20);
4476
+                RTL_W8(tp, 0xD1, 0x20);
4477
 
4478
                 if (dev->mtu > ETH_DATA_LEN) {
4479
-                        RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4480
-                        RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
4481
+                        RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4482
+                        RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
4483
 
4484
                         set_offset79(tp, 0x20);
4485
                 } else {
4486
-                        RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4487
-                        RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
4488
+                        RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4489
+                        RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
4490
 
4491
                         set_offset79(tp, 0x50);
4492
                 }
4493
@@ -26533,43 +26595,43 @@
4494
                 /* disable clock request. */
4495
                 pci_write_config_byte(pdev, 0x81, 0x00);
4496
 
4497
-                RTL_W8(Config3, RTL_R8(Config3) & ~BIT_4);
4498
-                RTL_W8(DBG_reg, RTL_R8(DBG_reg) | BIT_7 | BIT_1);
4499
+                RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~BIT_4);
4500
+                RTL_W8(tp, DBG_reg, RTL_R8(tp, DBG_reg) | BIT_7 | BIT_1);
4501
 
4502
                 if (dev->mtu > ETH_DATA_LEN) {
4503
-                        RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4504
-                        RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
4505
+                        RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4506
+                        RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
4507
 
4508
                         set_offset79(tp, 0x20);
4509
                 } else {
4510
-                        RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4511
-                        RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
4512
+                        RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4513
+                        RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
4514
 
4515
                         set_offset79(tp, 0x50);
4516
                 }
4517
 
4518
-                RTL_W8(TDFNR, 0x8);
4519
+                RTL_W8(tp, TDFNR, 0x8);
4520
 
4521
         } else if (tp->mcfg == CFG_METHOD_10) {
4522
                 set_offset70F(tp, 0x27);
4523
 
4524
-                RTL_W8(DBG_reg, RTL_R8(DBG_reg) | BIT_7 | BIT_1);
4525
+                RTL_W8(tp, DBG_reg, RTL_R8(tp, DBG_reg) | BIT_7 | BIT_1);
4526
 
4527
                 if (dev->mtu > ETH_DATA_LEN) {
4528
-                        RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4529
-                        RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
4530
+                        RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4531
+                        RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
4532
 
4533
                         set_offset79(tp, 0x20);
4534
                 } else {
4535
-                        RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4536
-                        RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
4537
+                        RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4538
+                        RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
4539
 
4540
                         set_offset79(tp, 0x50);
4541
                 }
4542
 
4543
-                RTL_W8(TDFNR, 0x8);
4544
+                RTL_W8(tp, TDFNR, 0x8);
4545
 
4546
-                RTL_W8(Config1, RTL_R8(Config1) | 0x10);
4547
+                RTL_W8(tp, Config1, RTL_R8(tp, Config1) | 0x10);
4548
 
4549
                 /* disable clock request. */
4550
                 pci_write_config_byte(pdev, 0x81, 0x00);
4551
@@ -26578,26 +26640,26 @@
4552
                 set_offset79(tp, 0x50);
4553
 
4554
                 if (dev->mtu > ETH_DATA_LEN)
4555
-                        RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4556
+                        RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4557
                 else
4558
-                        RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4559
+                        RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4560
 
4561
                 pci_write_config_byte(pdev, 0x81, 0x00);
4562
 
4563
-                RTL_W8(Config1, RTL_R8(Config1) | 0x10);
4564
+                RTL_W8(tp, Config1, RTL_R8(tp, Config1) | 0x10);
4565
 
4566
         } else if (tp->mcfg == CFG_METHOD_12) {
4567
                 set_offset70F(tp, 0x27);
4568
                 set_offset79(tp, 0x50);
4569
 
4570
                 if (dev->mtu > ETH_DATA_LEN)
4571
-                        RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4572
+                        RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4573
                 else
4574
-                        RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4575
+                        RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4576
 
4577
                 pci_write_config_byte(pdev, 0x81, 0x01);
4578
 
4579
-                RTL_W8(Config1, RTL_R8(Config1) | 0x10);
4580
+                RTL_W8(tp, Config1, RTL_R8(tp, Config1) | 0x10);
4581
 
4582
         } else if (tp->mcfg == CFG_METHOD_14 || tp->mcfg == CFG_METHOD_15) {
4583
 
4584
@@ -26605,79 +26667,79 @@
4585
                 set_offset79(tp, 0x50);
4586
 
4587
                 if (dev->mtu > ETH_DATA_LEN) {
4588
-                        RTL_W8(MTPS, 0x24);
4589
-                        RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4590
-                        RTL_W8(Config4, RTL_R8(Config4) | 0x01);
4591
+                        RTL_W8(tp, MTPS, 0x24);
4592
+                        RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4593
+                        RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01);
4594
                 } else {
4595
-                        RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4596
-                        RTL_W8(Config4, RTL_R8(Config4) & ~0x01);
4597
+                        RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4598
+                        RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);
4599
                 }
4600
 
4601
-                RTL_W8(0xF3, RTL_R8(0xF3) | BIT_5);
4602
-                RTL_W8(0xF3, RTL_R8(0xF3) & ~BIT_5);
4603
+                RTL_W8(tp, 0xF3, RTL_R8(tp, 0xF3) | BIT_5);
4604
+                RTL_W8(tp, 0xF3, RTL_R8(tp, 0xF3) & ~BIT_5);
4605
 
4606
-                RTL_W8(0xD0, RTL_R8(0xD0) | BIT_7 | BIT_6);
4607
+                RTL_W8(tp, 0xD0, RTL_R8(tp, 0xD0) | BIT_7 | BIT_6);
4608
 
4609
-                RTL_W8(0xD1, RTL_R8(0xD1) | BIT_2 | BIT_3);
4610
+                RTL_W8(tp, 0xD1, RTL_R8(tp, 0xD1) | BIT_2 | BIT_3);
4611
 
4612
-                RTL_W8(0xF1, RTL_R8(0xF1) | BIT_6 | BIT_5 | BIT_4 | BIT_2 | BIT_1);
4613
+                RTL_W8(tp, 0xF1, RTL_R8(tp, 0xF1) | BIT_6 | BIT_5 | BIT_4 | BIT_2 | BIT_1);
4614
 
4615
-                RTL_W8(TDFNR, 0x8);
4616
+                RTL_W8(tp, TDFNR, 0x8);
4617
 
4618
                 if (aspm)
4619
-                        RTL_W8(0xF1, RTL_R8(0xF1) | BIT_7);
4620
+                        RTL_W8(tp, 0xF1, RTL_R8(tp, 0xF1) | BIT_7);
4621
 
4622
-                RTL_W8(Config5, RTL_R8(Config5) & ~BIT_3);
4623
+                RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~BIT_3);
4624
 
4625
-                RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4626
+                RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4627
 
4628
-                RTL_W8(Config1, RTL_R8(Config1) & ~0x10);
4629
+                RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10);
4630
         } else if (tp->mcfg == CFG_METHOD_16 || tp->mcfg == CFG_METHOD_17) {
4631
                 set_offset70F(tp, 0x27);
4632
                 set_offset79(tp, 0x50);
4633
 
4634
-                rtl8168_eri_write(ioaddr, 0xC0, 2, 0x0000, ERIAR_ExGMAC);
4635
-                rtl8168_eri_write(ioaddr, 0xB8, 4, 0x00000000, ERIAR_ExGMAC);
4636
-                rtl8168_eri_write(ioaddr, 0xC8, 4, 0x00100002, ERIAR_ExGMAC);
4637
-                rtl8168_eri_write(ioaddr, 0xE8, 4, 0x00100006, ERIAR_ExGMAC);
4638
-                csi_tmp = rtl8168_eri_read(ioaddr, 0xD4, 4, ERIAR_ExGMAC);
4639
+                rtl8168_eri_write(tp, 0xC0, 2, 0x0000, ERIAR_ExGMAC);
4640
+                rtl8168_eri_write(tp, 0xB8, 4, 0x00000000, ERIAR_ExGMAC);
4641
+                rtl8168_eri_write(tp, 0xC8, 4, 0x00100002, ERIAR_ExGMAC);
4642
+                rtl8168_eri_write(tp, 0xE8, 4, 0x00100006, ERIAR_ExGMAC);
4643
+                csi_tmp = rtl8168_eri_read(tp, 0xD4, 4, ERIAR_ExGMAC);
4644
                 csi_tmp |= (BIT_8 | BIT_9 | BIT_10 | BIT_11 | BIT_12);
4645
-                rtl8168_eri_write(ioaddr, 0xD4, 4, csi_tmp, ERIAR_ExGMAC);
4646
-                csi_tmp = rtl8168_eri_read(ioaddr, 0x1D0, 4, ERIAR_ExGMAC);
4647
+                rtl8168_eri_write(tp, 0xD4, 4, csi_tmp, ERIAR_ExGMAC);
4648
+                csi_tmp = rtl8168_eri_read(tp, 0x1D0, 4, ERIAR_ExGMAC);
4649
                 csi_tmp |= BIT_1;
4650
-                rtl8168_eri_write(ioaddr, 0x1D0, 1, csi_tmp, ERIAR_ExGMAC);
4651
+                rtl8168_eri_write(tp, 0x1D0, 1, csi_tmp, ERIAR_ExGMAC);
4652
 
4653
-                csi_tmp = rtl8168_eri_read(ioaddr, 0xDC, 1, ERIAR_ExGMAC);
4654
+                csi_tmp = rtl8168_eri_read(tp, 0xDC, 1, ERIAR_ExGMAC);
4655
                 csi_tmp &= ~BIT_0;
4656
-                rtl8168_eri_write(ioaddr, 0xDC, 1, csi_tmp, ERIAR_ExGMAC);
4657
+                rtl8168_eri_write(tp, 0xDC, 1, csi_tmp, ERIAR_ExGMAC);
4658
                 csi_tmp |= BIT_0;
4659
-                rtl8168_eri_write(ioaddr, 0xDC, 1, csi_tmp, ERIAR_ExGMAC);
4660
+                rtl8168_eri_write(tp, 0xDC, 1, csi_tmp, ERIAR_ExGMAC);
4661
 
4662
-                RTL_W32(TxConfig, RTL_R32(TxConfig) | BIT_7);
4663
-                RTL_W8(0xD3, RTL_R8(0xD3) & ~BIT_7);
4664
-                RTL_W8(0x1B, RTL_R8(0x1B) & ~0x07);
4665
+                RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | BIT_7);
4666
+                RTL_W8(tp, 0xD3, RTL_R8(tp, 0xD3) & ~BIT_7);
4667
+                RTL_W8(tp, 0x1B, RTL_R8(tp, 0x1B) & ~0x07);
4668
 
4669
                 if (tp->mcfg == CFG_METHOD_16) {
4670
-                        RTL_W32(0xB0, 0xEE480010);
4671
-                        RTL_W8(0x1A, RTL_R8(0x1A) & ~(BIT_2|BIT_3));
4672
-                        rtl8168_eri_write(ioaddr, 0x1DC, 1, 0x64, ERIAR_ExGMAC);
4673
+                        RTL_W32(tp, 0xB0, 0xEE480010);
4674
+                        RTL_W8(tp, 0x1A, RTL_R8(tp, 0x1A) & ~(BIT_2|BIT_3));
4675
+                        rtl8168_eri_write(tp, 0x1DC, 1, 0x64, ERIAR_ExGMAC);
4676
                 } else {
4677
-                        csi_tmp = rtl8168_eri_read(ioaddr, 0x1B0, 4, ERIAR_ExGMAC);
4678
+                        csi_tmp = rtl8168_eri_read(tp, 0x1B0, 4, ERIAR_ExGMAC);
4679
                         csi_tmp |= BIT_4;
4680
-                        rtl8168_eri_write(ioaddr, 0x1B0, 1, csi_tmp, ERIAR_ExGMAC);
4681
-                        rtl8168_eri_write(ioaddr, 0xCC, 4, 0x00000050, ERIAR_ExGMAC);
4682
-                        rtl8168_eri_write(ioaddr, 0xD0, 4, 0x07ff0060, ERIAR_ExGMAC);
4683
+                        rtl8168_eri_write(tp, 0x1B0, 1, csi_tmp, ERIAR_ExGMAC);
4684
+                        rtl8168_eri_write(tp, 0xCC, 4, 0x00000050, ERIAR_ExGMAC);
4685
+                        rtl8168_eri_write(tp, 0xD0, 4, 0x07ff0060, ERIAR_ExGMAC);
4686
                 }
4687
 
4688
-                RTL_W8(TDFNR, 0x8);
4689
+                RTL_W8(tp, TDFNR, 0x8);
4690
 
4691
-                RTL_W8(Config2, RTL_R8(Config2) & ~PMSTS_En);
4692
+                RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~PMSTS_En);
4693
 
4694
-                RTL_W8(0xD0, RTL_R8(0xD0) | BIT_6);
4695
-                RTL_W8(0xF2, RTL_R8(0xF2) | BIT_6);
4696
+                RTL_W8(tp, 0xD0, RTL_R8(tp, 0xD0) | BIT_6);
4697
+                RTL_W8(tp, 0xF2, RTL_R8(tp, 0xF2) | BIT_6);
4698
 
4699
                 if (dev->mtu > ETH_DATA_LEN)
4700
-                        RTL_W8(MTPS, 0x27);
4701
+                        RTL_W8(tp, MTPS, 0x27);
4702
 
4703
                 /* disable clock request. */
4704
                 pci_write_config_byte(pdev, 0x81, 0x00);
4705
@@ -26686,80 +26748,80 @@
4706
                 set_offset70F(tp, 0x27);
4707
                 set_offset79(tp, 0x50);
4708
 
4709
-                rtl8168_eri_write(ioaddr, 0xC8, 4, 0x00100002, ERIAR_ExGMAC);
4710
-                rtl8168_eri_write(ioaddr, 0xE8, 4, 0x00100006, ERIAR_ExGMAC);
4711
-                RTL_W32(TxConfig, RTL_R32(TxConfig) | BIT_7);
4712
-                RTL_W8(0xD3, RTL_R8(0xD3) & ~BIT_7);
4713
-                csi_tmp = rtl8168_eri_read(ioaddr, 0xDC, 1, ERIAR_ExGMAC);
4714
+                rtl8168_eri_write(tp, 0xC8, 4, 0x00100002, ERIAR_ExGMAC);
4715
+                rtl8168_eri_write(tp, 0xE8, 4, 0x00100006, ERIAR_ExGMAC);
4716
+                RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | BIT_7);
4717
+                RTL_W8(tp, 0xD3, RTL_R8(tp, 0xD3) & ~BIT_7);
4718
+                csi_tmp = rtl8168_eri_read(tp, 0xDC, 1, ERIAR_ExGMAC);
4719
                 csi_tmp &= ~BIT_0;
4720
-                rtl8168_eri_write(ioaddr, 0xDC, 1, csi_tmp, ERIAR_ExGMAC);
4721
+                rtl8168_eri_write(tp, 0xDC, 1, csi_tmp, ERIAR_ExGMAC);
4722
                 csi_tmp |= BIT_0;
4723
-                rtl8168_eri_write(ioaddr, 0xDC, 1, csi_tmp, ERIAR_ExGMAC);
4724
+                rtl8168_eri_write(tp, 0xDC, 1, csi_tmp, ERIAR_ExGMAC);
4725
 
4726
                 if (aspm)
4727
-                        RTL_W8(0xF1, RTL_R8(0xF1) | BIT_7);
4728
+                        RTL_W8(tp, 0xF1, RTL_R8(tp, 0xF1) | BIT_7);
4729
 
4730
                 if (dev->mtu > ETH_DATA_LEN)
4731
-                        RTL_W8(MTPS, 0x27);
4732
+                        RTL_W8(tp, MTPS, 0x27);
4733
 
4734
-                RTL_W8(TDFNR, 0x8);
4735
+                RTL_W8(tp, TDFNR, 0x8);
4736
 
4737
-                RTL_W8(0xD0, RTL_R8(0xD0) | BIT_6);
4738
-                RTL_W8(0xF2, RTL_R8(0xF2) | BIT_6);
4739
+                RTL_W8(tp, 0xD0, RTL_R8(tp, 0xD0) | BIT_6);
4740
+                RTL_W8(tp, 0xF2, RTL_R8(tp, 0xF2) | BIT_6);
4741
 
4742
-                rtl8168_eri_write(ioaddr, 0xC0, 2, 0x0000, ERIAR_ExGMAC);
4743
-                rtl8168_eri_write(ioaddr, 0xB8, 4, 0x00000000, ERIAR_ExGMAC);
4744
-                csi_tmp = rtl8168_eri_read(ioaddr, 0xD4, 4, ERIAR_ExGMAC);
4745
+                rtl8168_eri_write(tp, 0xC0, 2, 0x0000, ERIAR_ExGMAC);
4746
+                rtl8168_eri_write(tp, 0xB8, 4, 0x00000000, ERIAR_ExGMAC);
4747
+                csi_tmp = rtl8168_eri_read(tp, 0xD4, 4, ERIAR_ExGMAC);
4748
                 csi_tmp |= (BIT_8 | BIT_9 | BIT_10 | BIT_11 | BIT_12);
4749
-                rtl8168_eri_write(ioaddr, 0xD4, 4, csi_tmp, ERIAR_ExGMAC);
4750
-                RTL_W8(0x1B,RTL_R8(0x1B) & ~0x07);
4751
+                rtl8168_eri_write(tp, 0xD4, 4, csi_tmp, ERIAR_ExGMAC);
4752
+                RTL_W8(tp, 0x1B,RTL_R8(tp, 0x1B) & ~0x07);
4753
 
4754
-                csi_tmp = rtl8168_eri_read(ioaddr, 0x1B0, 1, ERIAR_ExGMAC);
4755
+                csi_tmp = rtl8168_eri_read(tp, 0x1B0, 1, ERIAR_ExGMAC);
4756
                 csi_tmp |= BIT_4;
4757
-                rtl8168_eri_write(ioaddr, 0x1B0, 1, csi_tmp, ERIAR_ExGMAC);
4758
-                csi_tmp = rtl8168_eri_read(ioaddr, 0x1d0, 1, ERIAR_ExGMAC);
4759
+                rtl8168_eri_write(tp, 0x1B0, 1, csi_tmp, ERIAR_ExGMAC);
4760
+                csi_tmp = rtl8168_eri_read(tp, 0x1d0, 1, ERIAR_ExGMAC);
4761
                 csi_tmp |= BIT_4 | BIT_1;
4762
-                rtl8168_eri_write(ioaddr, 0x1d0, 1, csi_tmp, ERIAR_ExGMAC);
4763
-                rtl8168_eri_write(ioaddr, 0xCC, 4, 0x00000050, ERIAR_ExGMAC);
4764
-                rtl8168_eri_write(ioaddr, 0xd0, 4, 0x00000060, ERIAR_ExGMAC);
4765
+                rtl8168_eri_write(tp, 0x1d0, 1, csi_tmp, ERIAR_ExGMAC);
4766
+                rtl8168_eri_write(tp, 0xCC, 4, 0x00000050, ERIAR_ExGMAC);
4767
+                rtl8168_eri_write(tp, 0xd0, 4, 0x00000060, ERIAR_ExGMAC);
4768
         } else if (tp->mcfg == CFG_METHOD_20) {
4769
                 set_offset70F(tp, 0x27);
4770
                 set_offset79(tp, 0x50);
4771
 
4772
-                rtl8168_eri_write(ioaddr, 0xC8, 4, 0x00100002, ERIAR_ExGMAC);
4773
-                rtl8168_eri_write(ioaddr, 0xE8, 4, 0x00100006, ERIAR_ExGMAC);
4774
-                RTL_W32(TxConfig, RTL_R32(TxConfig) | BIT_7);
4775
-                RTL_W8(0xD3, RTL_R8(0xD3) & ~BIT_7);
4776
-                csi_tmp = rtl8168_eri_read(ioaddr, 0xDC, 1, ERIAR_ExGMAC);
4777
+                rtl8168_eri_write(tp, 0xC8, 4, 0x00100002, ERIAR_ExGMAC);
4778
+                rtl8168_eri_write(tp, 0xE8, 4, 0x00100006, ERIAR_ExGMAC);
4779
+                RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | BIT_7);
4780
+                RTL_W8(tp, 0xD3, RTL_R8(tp, 0xD3) & ~BIT_7);
4781
+                csi_tmp = rtl8168_eri_read(tp, 0xDC, 1, ERIAR_ExGMAC);
4782
                 csi_tmp &= ~BIT_0;
4783
-                rtl8168_eri_write(ioaddr, 0xDC, 1, csi_tmp, ERIAR_ExGMAC);
4784
+                rtl8168_eri_write(tp, 0xDC, 1, csi_tmp, ERIAR_ExGMAC);
4785
                 csi_tmp |= BIT_0;
4786
-                rtl8168_eri_write(ioaddr, 0xDC, 1, csi_tmp, ERIAR_ExGMAC);
4787
+                rtl8168_eri_write(tp, 0xDC, 1, csi_tmp, ERIAR_ExGMAC);
4788
 
4789
                 if (aspm)
4790
-                        RTL_W8(0xF1, RTL_R8(0xF1) | BIT_7);
4791
+                        RTL_W8(tp, 0xF1, RTL_R8(tp, 0xF1) | BIT_7);
4792
 
4793
                 if (dev->mtu > ETH_DATA_LEN)
4794
-                        RTL_W8(MTPS, 0x27);
4795
+                        RTL_W8(tp, MTPS, 0x27);
4796
 
4797
-                RTL_W8(TDFNR, 0x8);
4798
+                RTL_W8(tp, TDFNR, 0x8);
4799
 
4800
-                RTL_W8(0xD0, RTL_R8(0xD0) | BIT_6);
4801
-                RTL_W8(0xF2, RTL_R8(0xF2) | BIT_6);
4802
-                rtl8168_eri_write(ioaddr, 0xC0, 2, 0x0000, ERIAR_ExGMAC);
4803
-                rtl8168_eri_write(ioaddr, 0xB8, 4, 0x00000000, ERIAR_ExGMAC);
4804
-                csi_tmp = rtl8168_eri_read(ioaddr, 0xD4, 4, ERIAR_ExGMAC);
4805
+                RTL_W8(tp, 0xD0, RTL_R8(tp, 0xD0) | BIT_6);
4806
+                RTL_W8(tp, 0xF2, RTL_R8(tp, 0xF2) | BIT_6);
4807
+                rtl8168_eri_write(tp, 0xC0, 2, 0x0000, ERIAR_ExGMAC);
4808
+                rtl8168_eri_write(tp, 0xB8, 4, 0x00000000, ERIAR_ExGMAC);
4809
+                csi_tmp = rtl8168_eri_read(tp, 0xD4, 4, ERIAR_ExGMAC);
4810
                 csi_tmp |= BIT_10 | BIT_11;
4811
-                rtl8168_eri_write(ioaddr, 0xD4, 4, csi_tmp, ERIAR_ExGMAC);
4812
+                rtl8168_eri_write(tp, 0xD4, 4, csi_tmp, ERIAR_ExGMAC);
4813
 
4814
-                csi_tmp = rtl8168_eri_read(ioaddr, 0x1B0, 1, ERIAR_ExGMAC);
4815
+                csi_tmp = rtl8168_eri_read(tp, 0x1B0, 1, ERIAR_ExGMAC);
4816
                 csi_tmp |= BIT_4;
4817
-                rtl8168_eri_write(ioaddr, 0x1B0, 1, csi_tmp, ERIAR_ExGMAC);
4818
-                csi_tmp = rtl8168_eri_read(ioaddr, 0x1d0, 1, ERIAR_ExGMAC);
4819
+                rtl8168_eri_write(tp, 0x1B0, 1, csi_tmp, ERIAR_ExGMAC);
4820
+                csi_tmp = rtl8168_eri_read(tp, 0x1d0, 1, ERIAR_ExGMAC);
4821
                 csi_tmp |= BIT_4 | BIT_1;
4822
-                rtl8168_eri_write(ioaddr, 0x1d0, 1, csi_tmp, ERIAR_ExGMAC);
4823
-                rtl8168_eri_write(ioaddr, 0xCC, 4, 0x00000050, ERIAR_ExGMAC);
4824
-                rtl8168_eri_write(ioaddr, 0xd0, 4, 0x00000060, ERIAR_ExGMAC);
4825
+                rtl8168_eri_write(tp, 0x1d0, 1, csi_tmp, ERIAR_ExGMAC);
4826
+                rtl8168_eri_write(tp, 0xCC, 4, 0x00000050, ERIAR_ExGMAC);
4827
+                rtl8168_eri_write(tp, 0xd0, 4, 0x00000060, ERIAR_ExGMAC);
4828
         } else if (tp->mcfg == CFG_METHOD_21 || tp->mcfg == CFG_METHOD_22 ||
4829
                    tp->mcfg == CFG_METHOD_24 || tp->mcfg == CFG_METHOD_25 ||
4830
                    tp->mcfg == CFG_METHOD_26 || tp->mcfg == CFG_METHOD_29 ||
4831
@@ -26769,18 +26831,18 @@
4832
                 if (tp->mcfg == CFG_METHOD_21 || tp->mcfg == CFG_METHOD_22)
4833
                         set_offset711(tp, 0x04);
4834
 
4835
-                rtl8168_eri_write(ioaddr, 0xC8, 4, 0x00080002, ERIAR_ExGMAC);
4836
-                rtl8168_eri_write(ioaddr, 0xCC, 1, 0x38, ERIAR_ExGMAC);
4837
-                rtl8168_eri_write(ioaddr, 0xD0, 1, 0x48, ERIAR_ExGMAC);
4838
-                rtl8168_eri_write(ioaddr, 0xE8, 4, 0x00100006, ERIAR_ExGMAC);
4839
+                rtl8168_eri_write(tp, 0xC8, 4, 0x00080002, ERIAR_ExGMAC);
4840
+                rtl8168_eri_write(tp, 0xCC, 1, 0x38, ERIAR_ExGMAC);
4841
+                rtl8168_eri_write(tp, 0xD0, 1, 0x48, ERIAR_ExGMAC);
4842
+                rtl8168_eri_write(tp, 0xE8, 4, 0x00100006, ERIAR_ExGMAC);
4843
 
4844
-                RTL_W32(TxConfig, RTL_R32(TxConfig) | BIT_7);
4845
+                RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | BIT_7);
4846
 
4847
-                csi_tmp = rtl8168_eri_read(ioaddr, 0xDC, 1, ERIAR_ExGMAC);
4848
+                csi_tmp = rtl8168_eri_read(tp, 0xDC, 1, ERIAR_ExGMAC);
4849
                 csi_tmp &= ~BIT_0;
4850
-                rtl8168_eri_write(ioaddr, 0xDC, 1, csi_tmp, ERIAR_ExGMAC);
4851
+                rtl8168_eri_write(tp, 0xDC, 1, csi_tmp, ERIAR_ExGMAC);
4852
                 csi_tmp |= BIT_0;
4853
-                rtl8168_eri_write(ioaddr, 0xDC, 1, csi_tmp, ERIAR_ExGMAC);
4854
+                rtl8168_eri_write(tp, 0xDC, 1, csi_tmp, ERIAR_ExGMAC);
4855
 
4856
                 if (tp->mcfg == CFG_METHOD_26) {
4857
                         mac_ocp_data = rtl8168_mac_ocp_read(tp, 0xD3C0);
4858
@@ -26824,45 +26886,45 @@
4859
                         rtl8168_mac_ocp_write(tp, 0xE0D6, mac_ocp_data);
4860
                 }
4861
 
4862
-                RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4863
+                RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4864
 
4865
-                RTL_W8(0x1B, RTL_R8(0x1B) & ~0x07);
4866
+                RTL_W8(tp, 0x1B, RTL_R8(tp, 0x1B) & ~0x07);
4867
 
4868
-                RTL_W8(TDFNR, 0x4);
4869
+                RTL_W8(tp, TDFNR, 0x4);
4870
 
4871
-                RTL_W8(Config2, RTL_R8(Config2) & ~PMSTS_En);
4872
+                RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~PMSTS_En);
4873
 
4874
                 if (aspm)
4875
-                        RTL_W8(0xF1, RTL_R8(0xF1) | BIT_7);
4876
+                        RTL_W8(tp, 0xF1, RTL_R8(tp, 0xF1) | BIT_7);
4877
 
4878
                 if (dev->mtu > ETH_DATA_LEN)
4879
-                        RTL_W8(MTPS, 0x27);
4880
+                        RTL_W8(tp, MTPS, 0x27);
4881
 
4882
-                RTL_W8(0xD0, RTL_R8(0xD0) | BIT_6);
4883
-                RTL_W8(0xF2, RTL_R8(0xF2) | BIT_6);
4884
+                RTL_W8(tp, 0xD0, RTL_R8(tp, 0xD0) | BIT_6);
4885
+                RTL_W8(tp, 0xF2, RTL_R8(tp, 0xF2) | BIT_6);
4886
 
4887
-                RTL_W8(0xD0, RTL_R8(0xD0) | BIT_7);
4888
+                RTL_W8(tp, 0xD0, RTL_R8(tp, 0xD0) | BIT_7);
4889
 
4890
-                rtl8168_eri_write(ioaddr, 0xC0, 2, 0x0000, ERIAR_ExGMAC);
4891
-                rtl8168_eri_write(ioaddr, 0xB8, 4, 0x00000000, ERIAR_ExGMAC);
4892
+                rtl8168_eri_write(tp, 0xC0, 2, 0x0000, ERIAR_ExGMAC);
4893
+                rtl8168_eri_write(tp, 0xB8, 4, 0x00000000, ERIAR_ExGMAC);
4894
 
4895
                 if (tp->mcfg == CFG_METHOD_29 || tp->mcfg == CFG_METHOD_30)
4896
                         rtl8168_mac_ocp_write(tp, 0xE054, 0xFC01);
4897
 
4898
-                rtl8168_eri_write(ioaddr, 0x5F0, 2, 0x4F87, ERIAR_ExGMAC);
4899
+                rtl8168_eri_write(tp, 0x5F0, 2, 0x4F87, ERIAR_ExGMAC);
4900
 
4901
                 if (tp->mcfg == CFG_METHOD_29 || tp->mcfg == CFG_METHOD_30) {
4902
-                        csi_tmp = rtl8168_eri_read(ioaddr, 0xD4, 4, ERIAR_ExGMAC);
4903
+                        csi_tmp = rtl8168_eri_read(tp, 0xD4, 4, ERIAR_ExGMAC);
4904
                         csi_tmp |= (BIT_8 | BIT_9 | BIT_10 | BIT_11 | BIT_12);
4905
-                        rtl8168_eri_write(ioaddr, 0xD4, 4, csi_tmp, ERIAR_ExGMAC);
4906
+                        rtl8168_eri_write(tp, 0xD4, 4, csi_tmp, ERIAR_ExGMAC);
4907
 
4908
-                        csi_tmp = rtl8168_eri_read(ioaddr, 0xDC, 4, ERIAR_ExGMAC);
4909
+                        csi_tmp = rtl8168_eri_read(tp, 0xDC, 4, ERIAR_ExGMAC);
4910
                         csi_tmp |= (BIT_2 | BIT_3 | BIT_4);
4911
-                        rtl8168_eri_write(ioaddr, 0xDC, 4, csi_tmp, ERIAR_ExGMAC);
4912
+                        rtl8168_eri_write(tp, 0xDC, 4, csi_tmp, ERIAR_ExGMAC);
4913
                 } else {
4914
-                        csi_tmp = rtl8168_eri_read(ioaddr, 0xD4, 4, ERIAR_ExGMAC);
4915
+                        csi_tmp = rtl8168_eri_read(tp, 0xD4, 4, ERIAR_ExGMAC);
4916
                         csi_tmp |= (BIT_7 | BIT_8 | BIT_9 | BIT_10 | BIT_11 | BIT_12);
4917
-                        rtl8168_eri_write(ioaddr, 0xD4, 4, csi_tmp, ERIAR_ExGMAC);
4918
+                        rtl8168_eri_write(tp, 0xD4, 4, csi_tmp, ERIAR_ExGMAC);
4919
                 }
4920
 
4921
                 if (tp->mcfg == CFG_METHOD_21 || tp->mcfg == CFG_METHOD_22 ||
4922
@@ -26873,83 +26935,83 @@
4923
                         rtl8168_mac_ocp_write(tp, 0xC142, 0xFFFF);
4924
                 }
4925
 
4926
-                csi_tmp = rtl8168_eri_read(ioaddr, 0x1B0, 4, ERIAR_ExGMAC);
4927
+                csi_tmp = rtl8168_eri_read(tp, 0x1B0, 4, ERIAR_ExGMAC);
4928
                 csi_tmp &= ~BIT_12;
4929
-                rtl8168_eri_write(ioaddr, 0x1B0, 4, csi_tmp, ERIAR_ExGMAC);
4930
+                rtl8168_eri_write(tp, 0x1B0, 4, csi_tmp, ERIAR_ExGMAC);
4931
 
4932
                 if (tp->mcfg == CFG_METHOD_29 || tp->mcfg == CFG_METHOD_30) {
4933
-                        csi_tmp = rtl8168_eri_read(ioaddr, 0x2FC, 1, ERIAR_ExGMAC);
4934
+                        csi_tmp = rtl8168_eri_read(tp, 0x2FC, 1, ERIAR_ExGMAC);
4935
                         csi_tmp &= ~(BIT_2);
4936
-                        rtl8168_eri_write(ioaddr, 0x2FC, 1, csi_tmp, ERIAR_ExGMAC);
4937
+                        rtl8168_eri_write(tp, 0x2FC, 1, csi_tmp, ERIAR_ExGMAC);
4938
                 } else {
4939
-                        csi_tmp = rtl8168_eri_read(ioaddr, 0x2FC, 1, ERIAR_ExGMAC);
4940
+                        csi_tmp = rtl8168_eri_read(tp, 0x2FC, 1, ERIAR_ExGMAC);
4941
                         csi_tmp &= ~(BIT_0 | BIT_1 | BIT_2);
4942
                         csi_tmp |= BIT_0;
4943
-                        rtl8168_eri_write(ioaddr, 0x2FC, 1, csi_tmp, ERIAR_ExGMAC);
4944
+                        rtl8168_eri_write(tp, 0x2FC, 1, csi_tmp, ERIAR_ExGMAC);
4945
                 }
4946
 
4947
-                csi_tmp = rtl8168_eri_read(ioaddr, 0x1D0, 1, ERIAR_ExGMAC);
4948
+                csi_tmp = rtl8168_eri_read(tp, 0x1D0, 1, ERIAR_ExGMAC);
4949
                 csi_tmp |= BIT_1;
4950
-                rtl8168_eri_write(ioaddr, 0x1D0, 1, csi_tmp, ERIAR_ExGMAC);
4951
+                rtl8168_eri_write(tp, 0x1D0, 1, csi_tmp, ERIAR_ExGMAC);
4952
         } else if (tp->mcfg == CFG_METHOD_23 || tp->mcfg == CFG_METHOD_27 ||
4953
                    tp->mcfg == CFG_METHOD_28) {
4954
                 set_offset70F(tp, 0x27);
4955
                 set_offset79(tp, 0x50);
4956
 
4957
-                rtl8168_eri_write(ioaddr, 0xC8, 4, 0x00080002, ERIAR_ExGMAC);
4958
-                rtl8168_eri_write(ioaddr, 0xCC, 1, 0x2F, ERIAR_ExGMAC);
4959
-                rtl8168_eri_write(ioaddr, 0xD0, 1, 0x5F, ERIAR_ExGMAC);
4960
-                rtl8168_eri_write(ioaddr, 0xE8, 4, 0x00100006, ERIAR_ExGMAC);
4961
+                rtl8168_eri_write(tp, 0xC8, 4, 0x00080002, ERIAR_ExGMAC);
4962
+                rtl8168_eri_write(tp, 0xCC, 1, 0x2F, ERIAR_ExGMAC);
4963
+                rtl8168_eri_write(tp, 0xD0, 1, 0x5F, ERIAR_ExGMAC);
4964
+                rtl8168_eri_write(tp, 0xE8, 4, 0x00100006, ERIAR_ExGMAC);
4965
 
4966
-                RTL_W32(TxConfig, RTL_R32(TxConfig) | BIT_7);
4967
+                RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | BIT_7);
4968
 
4969
-                csi_tmp = rtl8168_eri_read(ioaddr, 0xDC, 1, ERIAR_ExGMAC);
4970
+                csi_tmp = rtl8168_eri_read(tp, 0xDC, 1, ERIAR_ExGMAC);
4971
                 csi_tmp &= ~BIT_0;
4972
-                rtl8168_eri_write(ioaddr, 0xDC, 1, csi_tmp, ERIAR_ExGMAC);
4973
+                rtl8168_eri_write(tp, 0xDC, 1, csi_tmp, ERIAR_ExGMAC);
4974
                 csi_tmp |= BIT_0;
4975
-                rtl8168_eri_write(ioaddr, 0xDC, 1, csi_tmp, ERIAR_ExGMAC);
4976
+                rtl8168_eri_write(tp, 0xDC, 1, csi_tmp, ERIAR_ExGMAC);
4977
 
4978
-                RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4979
+                RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4980
 
4981
-                RTL_W8(0xD0, RTL_R8(0xD0) | BIT_6);
4982
-                RTL_W8(0xF2, RTL_R8(0xF2) | BIT_6);
4983
+                RTL_W8(tp, 0xD0, RTL_R8(tp, 0xD0) | BIT_6);
4984
+                RTL_W8(tp, 0xF2, RTL_R8(tp, 0xF2) | BIT_6);
4985
 
4986
-                RTL_W8(0xD0, RTL_R8(0xD0) | BIT_7);
4987
+                RTL_W8(tp, 0xD0, RTL_R8(tp, 0xD0) | BIT_7);
4988
 
4989
-                rtl8168_eri_write(ioaddr, 0xC0, 2, 0x0000, ERIAR_ExGMAC);
4990
-                rtl8168_eri_write(ioaddr, 0xB8, 4, 0x00000000, ERIAR_ExGMAC);
4991
-                RTL_W8(0x1B, RTL_R8(0x1B) & ~0x07);
4992
+                rtl8168_eri_write(tp, 0xC0, 2, 0x0000, ERIAR_ExGMAC);
4993
+                rtl8168_eri_write(tp, 0xB8, 4, 0x00000000, ERIAR_ExGMAC);
4994
+                RTL_W8(tp, 0x1B, RTL_R8(tp, 0x1B) & ~0x07);
4995
 
4996
-                RTL_W8(TDFNR, 0x4);
4997
+                RTL_W8(tp, TDFNR, 0x4);
4998
 
4999
                 if (aspm)
5000
-                        RTL_W8(0xF1, RTL_R8(0xF1) | BIT_7);
5001
+                        RTL_W8(tp, 0xF1, RTL_R8(tp, 0xF1) | BIT_7);
5002
 
5003
-                csi_tmp = rtl8168_eri_read(ioaddr, 0x1B0, 4, ERIAR_ExGMAC);
5004
+                csi_tmp = rtl8168_eri_read(tp, 0x1B0, 4, ERIAR_ExGMAC);
5005
                 csi_tmp &= ~BIT_12;
5006
-                rtl8168_eri_write(ioaddr, 0x1B0, 4, csi_tmp, ERIAR_ExGMAC);
5007
+                rtl8168_eri_write(tp, 0x1B0, 4, csi_tmp, ERIAR_ExGMAC);
5008
 
5009
-                csi_tmp = rtl8168_eri_read(ioaddr, 0x2FC, 1, ERIAR_ExGMAC);
5010
+                csi_tmp = rtl8168_eri_read(tp, 0x2FC, 1, ERIAR_ExGMAC);
5011
                 csi_tmp &= ~(BIT_0 | BIT_1 | BIT_2);
5012
                 csi_tmp |= BIT_0;
5013
-                rtl8168_eri_write(ioaddr, 0x2FC, 1, csi_tmp, ERIAR_ExGMAC);
5014
+                rtl8168_eri_write(tp, 0x2FC, 1, csi_tmp, ERIAR_ExGMAC);
5015
 
5016
-                csi_tmp = rtl8168_eri_read(ioaddr, 0x1D0, 1, ERIAR_ExGMAC);
5017
+                csi_tmp = rtl8168_eri_read(tp, 0x1D0, 1, ERIAR_ExGMAC);
5018
                 csi_tmp |= BIT_1;
5019
-                rtl8168_eri_write(ioaddr, 0x1D0, 1, csi_tmp, ERIAR_ExGMAC);
5020
+                rtl8168_eri_write(tp, 0x1D0, 1, csi_tmp, ERIAR_ExGMAC);
5021
 
5022
                 if (dev->mtu > ETH_DATA_LEN)
5023
-                        RTL_W8(MTPS, 0x27);
5024
+                        RTL_W8(tp, MTPS, 0x27);
5025
 
5026
                 if (tp->mcfg == CFG_METHOD_27 || tp->mcfg == CFG_METHOD_28) {
5027
                         rtl8168_oob_mutex_lock(tp);
5028
-                        rtl8168_eri_write(ioaddr, 0x5F0, 2, 0x4F87, ERIAR_ExGMAC);
5029
+                        rtl8168_eri_write(tp, 0x5F0, 2, 0x4F87, ERIAR_ExGMAC);
5030
                         rtl8168_oob_mutex_unlock(tp);
5031
                 }
5032
 
5033
-                csi_tmp = rtl8168_eri_read(ioaddr, 0xD4, 4, ERIAR_ExGMAC);
5034
+                csi_tmp = rtl8168_eri_read(tp, 0xD4, 4, ERIAR_ExGMAC);
5035
                 csi_tmp  |= ( BIT_7 | BIT_8 | BIT_9 | BIT_10 | BIT_11 | BIT_12 );
5036
-                rtl8168_eri_write(ioaddr, 0xD4, 4, csi_tmp, ERIAR_ExGMAC);
5037
+                rtl8168_eri_write(tp, 0xD4, 4, csi_tmp, ERIAR_ExGMAC);
5038
 
5039
                 rtl8168_mac_ocp_write(tp, 0xC140, 0xFFFF);
5040
                 rtl8168_mac_ocp_write(tp, 0xC142, 0xFFFF);
5041
@@ -26968,26 +27030,23 @@
5042
                         mac_ocp_data |= BIT_7;
5043
                         rtl8168_mac_ocp_write(tp, 0xE860, mac_ocp_data);
5044
                 }
5045
-
5046
-                rtl8168_set_dash_other_fun_dev_pci_cmd_register(tp, 0x07, 0x0E);
5047
-                rtl8168_set_dash_other_fun_dev_aspm_clkreq(tp, 3, 1, 0x0E);
5048
-                rtl8168_set_dash_other_fun_dev_state_change(tp, 0, 0x0E);
5049
-        } else if (tp->mcfg == CFG_METHOD_31 || tp->mcfg == CFG_METHOD_32) {
5050
+        } else if (tp->mcfg == CFG_METHOD_31 || tp->mcfg == CFG_METHOD_32 ||
5051
+                   tp->mcfg == CFG_METHOD_33) {
5052
                 set_offset70F(tp, 0x27);
5053
                 set_offset79(tp, 0x50);
5054
 
5055
-                rtl8168_eri_write(ioaddr, 0xC8, 4, 0x00080002, ERIAR_ExGMAC);
5056
-                rtl8168_eri_write(ioaddr, 0xCC, 1, 0x2F, ERIAR_ExGMAC);
5057
-                rtl8168_eri_write(ioaddr, 0xD0, 1, 0x5F, ERIAR_ExGMAC);
5058
-                rtl8168_eri_write(ioaddr, 0xE8, 4, 0x00100006, ERIAR_ExGMAC);
5059
+                rtl8168_eri_write(tp, 0xC8, 4, 0x00080002, ERIAR_ExGMAC);
5060
+                rtl8168_eri_write(tp, 0xCC, 1, 0x2F, ERIAR_ExGMAC);
5061
+                rtl8168_eri_write(tp, 0xD0, 1, 0x5F, ERIAR_ExGMAC);
5062
+                rtl8168_eri_write(tp, 0xE8, 4, 0x00100006, ERIAR_ExGMAC);
5063
 
5064
-                RTL_W32(TxConfig, RTL_R32(TxConfig) | BIT_7);
5065
+                RTL_W32(tp, TxConfig, RTL_R32(tp, TxConfig) | BIT_7);
5066
 
5067
-                csi_tmp = rtl8168_eri_read(ioaddr, 0xDC, 1, ERIAR_ExGMAC);
5068
+                csi_tmp = rtl8168_eri_read(tp, 0xDC, 1, ERIAR_ExGMAC);
5069
                 csi_tmp &= ~BIT_0;
5070
-                rtl8168_eri_write(ioaddr, 0xDC, 1, csi_tmp, ERIAR_ExGMAC);
5071
+                rtl8168_eri_write(tp, 0xDC, 1, csi_tmp, ERIAR_ExGMAC);
5072
                 csi_tmp |= BIT_0;
5073
-                rtl8168_eri_write(ioaddr, 0xDC, 1, csi_tmp, ERIAR_ExGMAC);
5074
+                rtl8168_eri_write(tp, 0xDC, 1, csi_tmp, ERIAR_ExGMAC);
5075
 
5076
                 if (tp->RequireAdjustUpsTxLinkPulseTiming) {
5077
                         mac_ocp_data = rtl8168_mac_ocp_read(tp, 0xD412);
5078
@@ -27005,7 +27064,7 @@
5079
                 rtl8168_oob_mutex_lock(tp);
5080
                 mac_ocp_data = rtl8168_mac_ocp_read(tp, 0xE052);
5081
                 mac_ocp_data |= BIT_0;
5082
-                if (tp->mcfg == CFG_METHOD_32)
5083
+                if (tp->mcfg == CFG_METHOD_32 || tp->mcfg == CFG_METHOD_33)
5084
                         mac_ocp_data |= BIT_3;
5085
                 else
5086
                         mac_ocp_data &= ~BIT_3;
5087
@@ -27017,63 +27076,55 @@
5088
                 mac_ocp_data |= 0x47F;
5089
                 rtl8168_mac_ocp_write(tp, 0xD420, mac_ocp_data);
5090
 
5091
-                RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5092
+                RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5093
 
5094
-                RTL_W8(0x1B, RTL_R8(0x1B) & ~0x07);
5095
+                RTL_W8(tp, 0x1B, RTL_R8(tp, 0x1B) & ~0x07);
5096
 
5097
-                RTL_W8(TDFNR, 0x4);
5098
+                RTL_W8(tp, TDFNR, 0x4);
5099
 
5100
-                RTL_W8(Config2, RTL_R8(Config2) & ~PMSTS_En);
5101
+                RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~PMSTS_En);
5102
 
5103
                 if (aspm)
5104
-                        RTL_W8(0xF1, RTL_R8(0xF1) | BIT_7);
5105
+                        RTL_W8(tp, 0xF1, RTL_R8(tp, 0xF1) | BIT_7);
5106
 
5107
                 if (dev->mtu > ETH_DATA_LEN)
5108
-                        RTL_W8(MTPS, 0x27);
5109
+                        RTL_W8(tp, MTPS, 0x27);
5110
 
5111
-                RTL_W8(0xD0, RTL_R8(0xD0) | BIT_6);
5112
-                RTL_W8(0xF2, RTL_R8(0xF2) | BIT_6);
5113
+                RTL_W8(tp, 0xD0, RTL_R8(tp, 0xD0) | BIT_6);
5114
+                RTL_W8(tp, 0xF2, RTL_R8(tp, 0xF2) | BIT_6);
5115
 
5116
-                RTL_W8(0xD0, RTL_R8(0xD0) | BIT_7);
5117
+                RTL_W8(tp, 0xD0, RTL_R8(tp, 0xD0) | BIT_7);
5118
 
5119
-                rtl8168_eri_write(ioaddr, 0xC0, 2, 0x0000, ERIAR_ExGMAC);
5120
-                rtl8168_eri_write(ioaddr, 0xB8, 4, 0x00000000, ERIAR_ExGMAC);
5121
+                rtl8168_eri_write(tp, 0xC0, 2, 0x0000, ERIAR_ExGMAC);
5122
+                rtl8168_eri_write(tp, 0xB8, 4, 0x00000000, ERIAR_ExGMAC);
5123
 
5124
                 rtl8168_oob_mutex_lock(tp);
5125
-                rtl8168_eri_write(ioaddr, 0x5F0, 2, 0x4F87, ERIAR_ExGMAC);
5126
+                rtl8168_eri_write(tp, 0x5F0, 2, 0x4F87, ERIAR_ExGMAC);
5127
                 rtl8168_oob_mutex_unlock(tp);
5128
 
5129
-                csi_tmp = rtl8168_eri_read(ioaddr, 0xD4, 4, ERIAR_ExGMAC);
5130
+                csi_tmp = rtl8168_eri_read(tp, 0xD4, 4, ERIAR_ExGMAC);
5131
                 csi_tmp |= (BIT_7 | BIT_8 | BIT_9 | BIT_10 | BIT_11 | BIT_12);
5132
-                if (tp->mcfg == CFG_METHOD_32) csi_tmp|= BIT_4;
5133
-                rtl8168_eri_write(ioaddr, 0xD4, 4, csi_tmp, ERIAR_ExGMAC);
5134
+                if (tp->mcfg == CFG_METHOD_32 || tp->mcfg == CFG_METHOD_33)
5135
+                        csi_tmp|= BIT_4;
5136
+                rtl8168_eri_write(tp, 0xD4, 4, csi_tmp, ERIAR_ExGMAC);
5137
 
5138
                 rtl8168_mac_ocp_write(tp, 0xC140, 0xFFFF);
5139
                 rtl8168_mac_ocp_write(tp, 0xC142, 0xFFFF);
5140
 
5141
-                csi_tmp = rtl8168_eri_read(ioaddr, 0x1B0, 4, ERIAR_ExGMAC);
5142
+                csi_tmp = rtl8168_eri_read(tp, 0x1B0, 4, ERIAR_ExGMAC);
5143
                 csi_tmp &= ~BIT_12;
5144
-                rtl8168_eri_write(ioaddr, 0x1B0, 4, csi_tmp, ERIAR_ExGMAC);
5145
+                rtl8168_eri_write(tp, 0x1B0, 4, csi_tmp, ERIAR_ExGMAC);
5146
 
5147
-                csi_tmp = rtl8168_eri_read(ioaddr, 0x2FC, 1, ERIAR_ExGMAC);
5148
+                csi_tmp = rtl8168_eri_read(tp, 0x2FC, 1, ERIAR_ExGMAC);
5149
                 csi_tmp &= ~(BIT_0 | BIT_1);
5150
                 csi_tmp |= BIT_0;
5151
-                rtl8168_eri_write(ioaddr, 0x2FC, 1, csi_tmp, ERIAR_ExGMAC);
5152
+                rtl8168_eri_write(tp, 0x2FC, 1, csi_tmp, ERIAR_ExGMAC);
5153
 
5154
-                csi_tmp = rtl8168_eri_read(ioaddr, 0x1D0, 1, ERIAR_ExGMAC);
5155
+                csi_tmp = rtl8168_eri_read(tp, 0x1D0, 1, ERIAR_ExGMAC);
5156
                 csi_tmp &= ~BIT_1;
5157
-                rtl8168_eri_write(ioaddr, 0x1D0, 1, csi_tmp, ERIAR_ExGMAC);
5158
-
5159
-                rtl8168_set_dash_other_fun_dev_aspm_clkreq(tp, 2, 1, 0xED);
5160
-                rtl8168_set_dash_other_fun_dev_state_change(tp, 3, 0x78);
5161
-                if (tp->DASH) {
5162
-                        rtl8168_set_dash_other_fun_dev_state_change(tp, 0, 0x85);
5163
-                        rtl8168_set_dash_other_fun_dev_pci_cmd_register(tp, 0x07, 0x85);
5164
-                } else {
5165
-                        rtl8168_set_dash_other_fun_dev_state_change(tp, 3, 0x85);
5166
-                }
5167
+                rtl8168_eri_write(tp, 0x1D0, 1, csi_tmp, ERIAR_ExGMAC);
5168
         } else if (tp->mcfg == CFG_METHOD_1) {
5169
-                RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5170
+                RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5171
 
5172
                 if (dev->mtu > ETH_DATA_LEN) {
5173
                         pci_read_config_byte(pdev, 0x69, &device_control);
5174
@@ -27087,7 +27138,7 @@
5175
                         pci_write_config_byte(pdev, 0x69, device_control);
5176
                 }
5177
         } else if (tp->mcfg == CFG_METHOD_2) {
5178
-                RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5179
+                RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5180
 
5181
                 if (dev->mtu > ETH_DATA_LEN) {
5182
                         pci_read_config_byte(pdev, 0x69, &device_control);
5183
@@ -27095,17 +27146,17 @@
5184
                         device_control |= 0x28;
5185
                         pci_write_config_byte(pdev, 0x69, device_control);
5186
 
5187
-                        RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
5188
+                        RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0));
5189
                 } else {
5190
                         pci_read_config_byte(pdev, 0x69, &device_control);
5191
                         device_control &= ~0x70;
5192
                         device_control |= 0x58;
5193
                         pci_write_config_byte(pdev, 0x69, device_control);
5194
 
5195
-                        RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
5196
+                        RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
5197
                 }
5198
         } else if (tp->mcfg == CFG_METHOD_3) {
5199
-                RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5200
+                RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5201
 
5202
                 if (dev->mtu > ETH_DATA_LEN) {
5203
                         pci_read_config_byte(pdev, 0x69, &device_control);
5204
@@ -27113,14 +27164,14 @@
5205
                         device_control |= 0x28;
5206
                         pci_write_config_byte(pdev, 0x69, device_control);
5207
 
5208
-                        RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
5209
+                        RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0));
5210
                 } else {
5211
                         pci_read_config_byte(pdev, 0x69, &device_control);
5212
                         device_control &= ~0x70;
5213
                         device_control |= 0x58;
5214
                         pci_write_config_byte(pdev, 0x69, device_control);
5215
 
5216
-                        RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
5217
+                        RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
5218
                 }
5219
         }
5220
 
5221
@@ -27144,7 +27195,7 @@
5222
             tp->mcfg == CFG_METHOD_23 || tp->mcfg == CFG_METHOD_24 ||
5223
             tp->mcfg == CFG_METHOD_25 || tp->mcfg == CFG_METHOD_26 ||
5224
             tp->mcfg == CFG_METHOD_27 || tp->mcfg == CFG_METHOD_28)
5225
-                rtl8168_eri_write(ioaddr, 0x2F8, 2, 0x1D8F, ERIAR_ExGMAC);
5226
+                rtl8168_eri_write(tp, 0x2F8, 2, 0x1D8F, ERIAR_ExGMAC);
5227
 
5228
         if (tp->bios_setting & BIT_28) {
5229
                 if (tp->mcfg == CFG_METHOD_18 || tp->mcfg == CFG_METHOD_19 ||
5230
@@ -27178,6 +27229,7 @@
5231
                 break;
5232
         case CFG_METHOD_31:
5233
         case CFG_METHOD_32:
5234
+        case CFG_METHOD_33:
5235
                 rtl8168_mac_ocp_write(tp, 0xE098, 0xC302);
5236
                 break;
5237
         }
5238
@@ -27195,6 +27247,7 @@
5239
         case CFG_METHOD_30:
5240
         case CFG_METHOD_31:
5241
         case CFG_METHOD_32:
5242
+        case CFG_METHOD_33:
5243
                 if (aspm) {
5244
                         rtl8168_init_pci_offset_99(tp);
5245
                 }
5246
@@ -27210,6 +27263,7 @@
5247
         case CFG_METHOD_30:
5248
         case CFG_METHOD_31:
5249
         case CFG_METHOD_32:
5250
+        case CFG_METHOD_33:
5251
                 if (aspm) {
5252
                         rtl8168_init_pci_offset_180(tp);
5253
                 }
5254
@@ -27221,7 +27275,7 @@
5255
                         ASF | Macdbgo_sel);
5256
 
5257
 #if LINUX_VERSION_CODE < KERNEL_VERSION(3,0,0)
5258
-        RTL_W16(CPlusCmd, tp->cp_cmd);
5259
+        RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5260
 #else
5261
         rtl8168_hw_set_features(dev, dev->features);
5262
 #endif
5263
@@ -27243,10 +27297,11 @@
5264
         case CFG_METHOD_29:
5265
         case CFG_METHOD_30:
5266
         case CFG_METHOD_31:
5267
-        case CFG_METHOD_32: {
5268
+        case CFG_METHOD_32:
5269
+        case CFG_METHOD_33: {
5270
                 int timeout;
5271
                 for (timeout = 0; timeout < 10; timeout++) {
5272
-                        if ((rtl8168_eri_read(ioaddr, 0x1AE, 2, ERIAR_ExGMAC) & BIT_13)==0)
5273
+                        if ((rtl8168_eri_read(tp, 0x1AE, 2, ERIAR_ExGMAC) & BIT_13)==0)
5274
                                 break;
5275
                         mdelay(1);
5276
                 }
5277
@@ -27254,7 +27309,7 @@
5278
         break;
5279
         }
5280
 
5281
-        RTL_W16(RxMaxSize, tp->rx_buf_sz);
5282
+        RTL_W16(tp, RxMaxSize, tp->rx_buf_sz);
5283
 
5284
         rtl8168_disable_rxdvgate(dev);
5285
 
5286
@@ -27314,12 +27369,13 @@
5287
         case CFG_METHOD_30:
5288
         case CFG_METHOD_31:
5289
         case CFG_METHOD_32:
5290
+        case CFG_METHOD_33:
5291
                 if (aspm) {
5292
-                        RTL_W8(Config5, RTL_R8(Config5) | BIT_0);
5293
-                        RTL_W8(Config2, RTL_R8(Config2) | BIT_7);
5294
+                        RTL_W8(tp, Config5, RTL_R8(tp, Config5) | BIT_0);
5295
+                        RTL_W8(tp, Config2, RTL_R8(tp, Config2) | BIT_7);
5296
                 } else {
5297
-                        RTL_W8(Config2, RTL_R8(Config2) & ~BIT_7);
5298
-                        RTL_W8(Config5, RTL_R8(Config5) & ~BIT_0);
5299
+                        RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~BIT_7);
5300
+                        RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~BIT_0);
5301
                 }
5302
                 break;
5303
         }
5304
@@ -27333,11 +27389,10 @@
5305
 rtl8168_hw_start(struct net_device *dev)
5306
 {
5307
         struct rtl8168_private *tp = netdev_priv(dev);
5308
-        void __iomem *ioaddr = tp->mmio_addr;
5309
 
5310
-        RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5311
+        RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
5312
 
5313
-        rtl8168_enable_hw_interrupt(tp, ioaddr);
5314
+        rtl8168_enable_hw_interrupt(tp);
5315
 }
5316
 
5317
 
5318
@@ -27414,8 +27469,8 @@
5319
 {
5320
         struct pci_dev *pdev = tp->pci_dev;
5321
 
5322
-        pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
5323
-                         PCI_DMA_FROMDEVICE);
5324
+        dma_unmap_single(&pdev->dev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
5325
+                         DMA_FROM_DEVICE);
5326
         dev_kfree_skb(*sk_buff);
5327
         *sk_buff = NULL;
5328
         rtl8168_make_unusable_by_asic(desc);
5329
@@ -27461,8 +27516,8 @@
5330
 
5331
         skb_reserve(skb, RTK_RX_ALIGN);
5332
 
5333
-        mapping = pci_map_single(tp->pci_dev, skb->data, rx_buf_sz,
5334
-                                 PCI_DMA_FROMDEVICE);
5335
+        mapping = dma_map_single(&tp->pci_dev->dev, skb->data, rx_buf_sz,
5336
+                                 DMA_FROM_DEVICE);
5337
         if (unlikely(dma_mapping_error(&tp->pci_dev->dev, mapping))) {
5338
                 if (unlikely(net_ratelimit()))
5339
                         netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
5340
@@ -27528,15 +27583,13 @@
5341
 static void
5342
 rtl8168_desc_addr_fill(struct rtl8168_private *tp)
5343
 {
5344
-        void __iomem *ioaddr = tp->mmio_addr;
5345
-
5346
         if (!tp->TxPhyAddr || !tp->RxPhyAddr)
5347
                 return;
5348
 
5349
-        RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr & DMA_BIT_MASK(32)));
5350
-        RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr >> 32));
5351
-        RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr & DMA_BIT_MASK(32)));
5352
-        RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr >> 32));
5353
+        RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr & DMA_BIT_MASK(32)));
5354
+        RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr >> 32));
5355
+        RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr & DMA_BIT_MASK(32)));
5356
+        RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr >> 32));
5357
 }
5358
 
5359
 static void
5360
@@ -27607,7 +27660,7 @@
5361
 {
5362
         unsigned int len = tx_skb->len;
5363
 
5364
-        pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
5365
+        dma_unmap_single(&pdev->dev, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5366
         desc->opts1 = 0x00;
5367
         desc->opts2 = 0x00;
5368
         desc->addr = 0x00;
5369
@@ -27673,6 +27726,9 @@
5370
 static void rtl8168_cancel_schedule_work(struct net_device *dev)
5371
 {
5372
         struct rtl8168_private *tp = netdev_priv(dev);
5373
+        struct work_struct *work = &tp->task.work;
5374
+
5375
+        if (!work->func) return;
5376
 
5377
         cancel_delayed_work_sync(&tp->task);
5378
 }
5379
@@ -27682,7 +27738,6 @@
5380
 rtl8168_wait_for_quiescence(struct net_device *dev)
5381
 {
5382
         struct rtl8168_private *tp = netdev_priv(dev);
5383
-        void __iomem *ioaddr = tp->mmio_addr;
5384
 
5385
         synchronize_irq(dev->irq);
5386
 
5387
@@ -27693,7 +27748,7 @@
5388
 #endif
5389
 #endif//CONFIG_R8168_NAPI
5390
 
5391
-        rtl8168_irq_mask_and_ack(tp, ioaddr);
5392
+        rtl8168_irq_mask_and_ack(tp);
5393
 
5394
 #ifdef CONFIG_R8168_NAPI
5395
 #if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0)
5396
@@ -27760,9 +27815,9 @@
5397
         rtl8168_wait_for_quiescence(dev);
5398
 
5399
 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24)
5400
-        rtl8168_rx_interrupt(dev, tp, tp->mmio_addr, &budget);
5401
+        rtl8168_rx_interrupt(dev, tp, &budget);
5402
 #else
5403
-        rtl8168_rx_interrupt(dev, tp, tp->mmio_addr, budget);
5404
+        rtl8168_rx_interrupt(dev, tp, budget);
5405
 #endif  //LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24)
5406
 
5407
         spin_lock_irqsave(&tp->lock, flags);
5408
@@ -27804,6 +27859,17 @@
5409
         rtl8168_schedule_work(dev, rtl8168_reset_task);
5410
 }
5411
 
5412
+static u32
5413
+rtl8168_get_txd_opts1(u32 opts1, u32 len, unsigned int entry)
5414
+{
5415
+        u32 status = opts1 | len;
5416
+
5417
+        if (entry == NUM_TX_DESC - 1)
5418
+                status |= RingEnd;
5419
+
5420
+        return status;
5421
+}
5422
+
5423
 static int
5424
 rtl8168_xmit_frags(struct rtl8168_private *tp,
5425
                    struct sk_buff *skb,
5426
@@ -27813,9 +27879,10 @@
5427
         struct skb_shared_info *info = skb_shinfo(skb);
5428
         unsigned int cur_frag, entry;
5429
         struct TxDesc *txd = NULL;
5430
+        const unsigned char nr_frags = info->nr_frags;
5431
 
5432
         entry = tp->cur_tx;
5433
-        for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
5434
+        for (cur_frag = 0; cur_frag < nr_frags; cur_frag++) {
5435
                 skb_frag_t *frag = info->frags + cur_frag;
5436
                 dma_addr_t mapping;
5437
                 u32 status, len;
5438
@@ -27831,7 +27898,7 @@
5439
                 len = skb_frag_size(frag);
5440
                 addr = skb_frag_address(frag);
5441
 #endif
5442
-                mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
5443
+                mapping = dma_map_single(&tp->pci_dev->dev, addr, len, DMA_TO_DEVICE);
5444
 
5445
                 if (unlikely(dma_mapping_error(&tp->pci_dev->dev, mapping))) {
5446
                         if (unlikely(net_ratelimit()))
5447
@@ -27841,20 +27908,19 @@
5448
                 }
5449
 
5450
                 /* anti gcc 2.95.3 bugware (sic) */
5451
-                status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
5452
+                status = rtl8168_get_txd_opts1(opts1, len, entry);
5453
+                if (cur_frag == (nr_frags - 1)) {
5454
+                        tp->tx_skb[entry].skb = skb;
5455
+                        status |= LastFrag;
5456
+                }
5457
 
5458
                 txd->addr = cpu_to_le64(mapping);
5459
 
5460
                 tp->tx_skb[entry].len = len;
5461
 
5462
-                txd->opts1 = cpu_to_le32(status);
5463
                 txd->opts2 = cpu_to_le32(opts2);
5464
-        }
5465
-
5466
-        if (cur_frag) {
5467
-                tp->tx_skb[entry].skb = skb;
5468
                 wmb();
5469
-                txd->opts1 |= cpu_to_le32(LastFrag);
5470
+                txd->opts1 = cpu_to_le32(status);
5471
         }
5472
 
5473
         return cur_frag;
5474
@@ -27976,7 +28042,7 @@
5475
         txd = tp->TxDescArray + entry;
5476
         len = ETH_ZLEN - skb->len;
5477
         addr = tp->ShortPacketEmptyBuffer;
5478
-        mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
5479
+        mapping = dma_map_single(&tp->pci_dev->dev, addr, len, DMA_TO_DEVICE);
5480
         if (unlikely(dma_mapping_error(&tp->pci_dev->dev, mapping))) {
5481
                 if (unlikely(net_ratelimit()))
5482
                         netif_err(tp, drv, tp->dev,
5483
@@ -27984,15 +28050,14 @@
5484
                 ret = -ENOMEM;
5485
                 goto out;
5486
         }
5487
-        status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
5488
+        status = rtl8168_get_txd_opts1(opts1, len, entry);
5489
+        status |= LastFrag;
5490
 
5491
         txd->addr = cpu_to_le64(mapping);
5492
 
5493
-        txd->opts1 = cpu_to_le32(status);
5494
         txd->opts2 = cpu_to_le32(opts2);
5495
-
5496
         wmb();
5497
-        txd->opts1 |= cpu_to_le32(LastFrag);
5498
+        txd->opts1 = cpu_to_le32(status);
5499
 out:
5500
         return ret;
5501
 }
5502
@@ -28068,7 +28133,6 @@
5503
         struct rtl8168_private *tp = netdev_priv(dev);
5504
         unsigned int entry;
5505
         struct TxDesc *txd;
5506
-        void __iomem *ioaddr = tp->mmio_addr;
5507
         dma_addr_t mapping;
5508
         u32 len;
5509
         u32 opts1;
5510
@@ -28182,8 +28246,8 @@
5511
                 }
5512
         }
5513
 
5514
-        opts1 |= len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
5515
-        mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
5516
+        opts1 = rtl8168_get_txd_opts1(opts1, len, entry);
5517
+        mapping = dma_map_single(&tp->pci_dev->dev, skb->data, len, DMA_TO_DEVICE);
5518
         if (unlikely(dma_mapping_error(&tp->pci_dev->dev, mapping))) {
5519
                 if (unlikely(net_ratelimit()))
5520
                         netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
5521
@@ -28192,7 +28256,6 @@
5522
         tp->tx_skb[entry].len = len;
5523
         txd->addr = cpu_to_le64(mapping);
5524
         txd->opts2 = cpu_to_le32(opts2);
5525
-        txd->opts1 = cpu_to_le32(opts1&~DescOwn);
5526
         wmb();
5527
         txd->opts1 = cpu_to_le32(opts1);
5528
 
5529
@@ -28206,7 +28269,7 @@
5530
 
5531
         wmb();
5532
 
5533
-        RTL_W8(TxPoll, NPQ);    /* set polling bit */
5534
+        RTL_W8(tp, TxPoll, NPQ);    /* set polling bit */
5535
 
5536
         if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
5537
                 netif_stop_queue(dev);
5538
@@ -28238,14 +28301,12 @@
5539
 
5540
 static void
5541
 rtl8168_tx_interrupt(struct net_device *dev,
5542
-                     struct rtl8168_private *tp,
5543
-                     void __iomem *ioaddr)
5544
+                     struct rtl8168_private *tp)
5545
 {
5546
         unsigned int dirty_tx, tx_left;
5547
 
5548
         assert(dev != NULL);
5549
         assert(tp != NULL);
5550
-        assert(ioaddr != NULL);
5551
 
5552
         dirty_tx = tp->dirty_tx;
5553
         smp_rmb();
5554
@@ -28290,7 +28351,7 @@
5555
                 }
5556
                 smp_rmb();
5557
                 if (tp->cur_tx != dirty_tx)
5558
-                        RTL_W8(TxPoll, NPQ);
5559
+                        RTL_W8(tp, TxPoll, NPQ);
5560
         }
5561
 }
5562
 
5563
@@ -28380,7 +28441,7 @@
5564
 static int
5565
 rtl8168_rx_interrupt(struct net_device *dev,
5566
                      struct rtl8168_private *tp,
5567
-                     void __iomem *ioaddr, napi_budget budget)
5568
+                     napi_budget budget)
5569
 {
5570
         unsigned int cur_rx, rx_left;
5571
         unsigned int delta, count = 0;
5572
@@ -28391,7 +28452,6 @@
5573
 
5574
         assert(dev != NULL);
5575
         assert(tp != NULL);
5576
-        assert(ioaddr != NULL);
5577
 
5578
         if ((tp->RxDescArray == NULL) || (tp->Rx_skbuff == NULL))
5579
                 goto rx_out;
5580
@@ -28428,8 +28488,6 @@
5581
                 } else {
5582
                         struct sk_buff *skb;
5583
                         int pkt_size;
5584
-                        void (*pci_action)(struct pci_dev *, dma_addr_t,
5585
-                                           size_t, int);
5586
 
5587
 process_pkt:
5588
                         if (likely(!(dev->features & NETIF_F_RXFCS)))
5589
@@ -28450,22 +28508,23 @@
5590
                         }
5591
 
5592
                         skb = tp->Rx_skbuff[entry];
5593
-                        if (tp->cp_cmd & RxChkSum)
5594
-                                rtl8168_rx_csum(tp, skb, desc);
5595
 
5596
-                        pci_dma_sync_single_for_cpu(tp->pci_dev,
5597
-                                                    le64_to_cpu(desc->addr), tp->rx_buf_sz,
5598
-                                                    PCI_DMA_FROMDEVICE);
5599
+                        dma_sync_single_for_cpu(&tp->pci_dev->dev,
5600
+                                                le64_to_cpu(desc->addr), tp->rx_buf_sz,
5601
+                                                DMA_FROM_DEVICE);
5602
 
5603
-                        pci_action = pci_dma_sync_single_for_device;
5604
                         if (rtl8168_try_rx_copy(tp, &skb, pkt_size,
5605
                                                 desc, tp->rx_buf_sz)) {
5606
-                                pci_action = pci_unmap_single;
5607
                                 tp->Rx_skbuff[entry] = NULL;
5608
+                                dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr),
5609
+                                                 tp->rx_buf_sz, DMA_FROM_DEVICE);
5610
+                        } else {
5611
+                                dma_sync_single_for_device(&tp->pci_dev->dev, le64_to_cpu(desc->addr),
5612
+                                                           tp->rx_buf_sz, DMA_FROM_DEVICE);
5613
                         }
5614
 
5615
-                        pci_action(tp->pci_dev, le64_to_cpu(desc->addr),
5616
-                                   tp->rx_buf_sz, PCI_DMA_FROMDEVICE);
5617
+                        if (tp->cp_cmd & RxChkSum)
5618
+                                rtl8168_rx_csum(tp, skb, desc);
5619
 
5620
                         skb->dev = dev;
5621
                         skb_put(skb, pkt_size);
5622
@@ -28525,12 +28584,11 @@
5623
 {
5624
         struct net_device *dev = (struct net_device *) dev_instance;
5625
         struct rtl8168_private *tp = netdev_priv(dev);
5626
-        void __iomem *ioaddr = tp->mmio_addr;
5627
         int status;
5628
         int handled = 0;
5629
 
5630
         do {
5631
-                status = RTL_R16(IntrStatus);
5632
+                status = RTL_R16(tp, IntrStatus);
5633
 
5634
                 if (!(tp->features & RTL_FEATURE_MSI)) {
5635
                         /* hotplug/major error/no more work/shared irq */
5636
@@ -28543,7 +28601,7 @@
5637
 
5638
                 handled = 1;
5639
 
5640
-                rtl8168_disable_hw_interrupt(tp, ioaddr);
5641
+                rtl8168_disable_hw_interrupt(tp);
5642
 
5643
                 switch (tp->mcfg) {
5644
                 case CFG_METHOD_9:
5645
@@ -28570,11 +28628,12 @@
5646
                 case CFG_METHOD_30:
5647
                 case CFG_METHOD_31:
5648
                 case CFG_METHOD_32:
5649
+                case CFG_METHOD_33:
5650
                         /* RX_OVERFLOW RE-START mechanism now HW handles it automatically*/
5651
-                        RTL_W16(IntrStatus, status&~RxFIFOOver);
5652
+                        RTL_W16(tp, IntrStatus, status&~RxFIFOOver);
5653
                         break;
5654
                 default:
5655
-                        RTL_W16(IntrStatus, status);
5656
+                        RTL_W16(tp, IntrStatus, status);
5657
                         break;
5658
                 }
5659
 
5660
@@ -28601,7 +28660,7 @@
5661
                                 if (status & ISRIMR_DASH_INTR_CMAC_RESET)
5662
                                         tp->CmacResetIntr = TRUE;
5663
 
5664
-                                DashIntType2Status = RTL_CMAC_R8(CMAC_IBISR0);
5665
+                                DashIntType2Status = RTL_CMAC_R8(tp, CMAC_IBISR0);
5666
                                 if (DashIntType2Status & ISRIMR_DASH_TYPE2_ROK) {
5667
                                         tp->RcvFwDashOkEvt = TRUE;
5668
                                 }
5669
@@ -28612,7 +28671,7 @@
5670
                                         tp->DashFwDisableRx = TRUE;
5671
                                 }
5672
 
5673
-                                RTL_CMAC_W8(CMAC_IBISR0, DashIntType2Status);
5674
+                                RTL_CMAC_W8(tp, CMAC_IBISR0, DashIntType2Status);
5675
                         } else {
5676
                                 if (status & ISRIMR_DP_REQSYS_OK) {
5677
                                         tp->RcvFwReqSysOkEvt = TRUE;
5678
@@ -28639,7 +28698,7 @@
5679
                                        dev->name, status);
5680
                 } else {
5681
                         tp->keep_intr_cnt = RTK_KEEP_INTERRUPT_COUNT;
5682
-                        rtl8168_switch_to_hw_interrupt(tp, ioaddr);
5683
+                        rtl8168_switch_to_hw_interrupt(tp);
5684
                 }
5685
 #else
5686
                 if (status & tp->intr_mask || tp->keep_intr_cnt-- > 0) {
5687
@@ -28648,11 +28707,11 @@
5688
                         if (status & tp->intr_mask)
5689
                                 tp->keep_intr_cnt = RTK_KEEP_INTERRUPT_COUNT;
5690
 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24)
5691
-                        rtl8168_rx_interrupt(dev, tp, tp->mmio_addr, &budget);
5692
+                        rtl8168_rx_interrupt(dev, tp, &budget);
5693
 #else
5694
-                        rtl8168_rx_interrupt(dev, tp, tp->mmio_addr, budget);
5695
+                        rtl8168_rx_interrupt(dev, tp, budget);
5696
 #endif  //LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24)
5697
-                        rtl8168_tx_interrupt(dev, tp, ioaddr);
5698
+                        rtl8168_tx_interrupt(dev, tp);
5699
 
5700
 #ifdef ENABLE_DASH_SUPPORT
5701
                         if ( tp->DASH ) {
5702
@@ -28662,10 +28721,10 @@
5703
                         }
5704
 #endif
5705
 
5706
-                        rtl8168_switch_to_timer_interrupt(tp, ioaddr);
5707
+                        rtl8168_switch_to_timer_interrupt(tp);
5708
                 } else {
5709
                         tp->keep_intr_cnt = RTK_KEEP_INTERRUPT_COUNT;
5710
-                        rtl8168_switch_to_hw_interrupt(tp, ioaddr);
5711
+                        rtl8168_switch_to_hw_interrupt(tp);
5712
                 }
5713
 #endif
5714
 
5715
@@ -28678,16 +28737,15 @@
5716
 static int rtl8168_poll(napi_ptr napi, napi_budget budget)
5717
 {
5718
         struct rtl8168_private *tp = RTL_GET_PRIV(napi, struct rtl8168_private);
5719
-        void __iomem *ioaddr = tp->mmio_addr;
5720
         RTL_GET_NETDEV(tp)
5721
         unsigned int work_to_do = RTL_NAPI_QUOTA(budget, dev);
5722
         unsigned int work_done;
5723
         unsigned long flags;
5724
 
5725
-        work_done = rtl8168_rx_interrupt(dev, tp, ioaddr, budget);
5726
+        work_done = rtl8168_rx_interrupt(dev, tp, budget);
5727
 
5728
         spin_lock_irqsave(&tp->lock, flags);
5729
-        rtl8168_tx_interrupt(dev, tp, ioaddr);
5730
+        rtl8168_tx_interrupt(dev, tp);
5731
         spin_unlock_irqrestore(&tp->lock, flags);
5732
 
5733
         RTL_NAPI_QUOTA_UPDATE(dev, work_done, budget);
5734
@@ -28716,7 +28774,7 @@
5735
                  */
5736
                 smp_wmb();
5737
 
5738
-                rtl8168_switch_to_timer_interrupt(tp, ioaddr);
5739
+                rtl8168_switch_to_timer_interrupt(tp);
5740
         }
5741
 
5742
         return RTL_NAPI_RETURN_VALUE;
5743
@@ -28726,15 +28784,14 @@
5744
 static void rtl8168_sleep_rx_enable(struct net_device *dev)
5745
 {
5746
         struct rtl8168_private *tp = netdev_priv(dev);
5747
-        void __iomem *ioaddr = tp->mmio_addr;
5748
 
5749
         if ((tp->mcfg == CFG_METHOD_1) || (tp->mcfg == CFG_METHOD_2)) {
5750
-                RTL_W8(ChipCmd, CmdReset);
5751
+                RTL_W8(tp, ChipCmd, CmdReset);
5752
                 rtl8168_rx_desc_offset0_init(tp, 0);
5753
-                RTL_W8(ChipCmd, CmdRxEnb);
5754
+                RTL_W8(tp, ChipCmd, CmdRxEnb);
5755
         } else if (tp->mcfg == CFG_METHOD_14 || tp->mcfg == CFG_METHOD_15) {
5756
-                rtl8168_ephy_write(ioaddr, 0x19, 0xFF64);
5757
-                RTL_W32(RxConfig, RTL_R32(RxConfig) | AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
5758
+                rtl8168_ephy_write(tp, 0x19, 0xFF64);
5759
+                RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) | AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
5760
         }
5761
 }
5762
 
5763
@@ -28804,16 +28861,16 @@
5764
 
5765
                 free_irq(dev->irq, dev);
5766
 
5767
-                pci_free_consistent(pdev, R8168_RX_RING_BYTES, tp->RxDescArray,
5768
-                                    tp->RxPhyAddr);
5769
-                pci_free_consistent(pdev, R8168_TX_RING_BYTES, tp->TxDescArray,
5770
-                                    tp->TxPhyAddr);
5771
+                dma_free_coherent(&pdev->dev, R8168_RX_RING_BYTES, tp->RxDescArray,
5772
+                                  tp->RxPhyAddr);
5773
+                dma_free_coherent(&pdev->dev, R8168_TX_RING_BYTES, tp->TxDescArray,
5774
+                                  tp->TxPhyAddr);
5775
                 tp->TxDescArray = NULL;
5776
                 tp->RxDescArray = NULL;
5777
 
5778
                 if (tp->ShortPacketEmptyBuffer != NULL) {
5779
-                        pci_free_consistent(pdev, SHORT_PACKET_PADDING_BUF_SIZE, tp->ShortPacketEmptyBuffer,
5780
-                                            tp->ShortPacketEmptyBufferPhy);
5781
+                        dma_free_coherent(&pdev->dev, SHORT_PACKET_PADDING_BUF_SIZE, tp->ShortPacketEmptyBuffer,
5782
+                                          tp->ShortPacketEmptyBufferPhy);
5783
                         tp->ShortPacketEmptyBuffer = NULL;
5784
                 }
5785
         } else {
5786
@@ -28835,7 +28892,7 @@
5787
         struct net_device *dev = pci_get_drvdata(pdev);
5788
         struct rtl8168_private *tp = netdev_priv(dev);
5789
 
5790
-        if (tp->DASH)
5791
+        if (HW_DASH_SUPPORT_DASH(tp))
5792
                 rtl8168_driver_stop(tp);
5793
 
5794
         rtl8168_set_bios_setting(dev);
5795
@@ -28925,7 +28982,7 @@
5796
         spin_unlock_irqrestore(&tp->lock, flags);
5797
 
5798
 out:
5799
-        if (tp->DASH) {
5800
+        if (HW_DASH_SUPPORT_DASH(tp)) {
5801
                 spin_lock_irqsave(&tp->lock, flags);
5802
                 rtl8168_driver_stop(tp);
5803
                 spin_unlock_irqrestore(&tp->lock, flags);
5804
@@ -28968,7 +29025,7 @@
5805
         spin_unlock_irqrestore(&tp->lock, flags);
5806
 
5807
         if (!netif_running(dev)) {
5808
-                if (tp->DASH) {
5809
+                if (HW_DASH_SUPPORT_DASH(tp)) {
5810
                         spin_lock_irqsave(&tp->lock, flags);
5811
                         rtl8168_driver_start(tp);
5812
                         spin_unlock_irqrestore(&tp->lock, flags);
5813
r8168-8.047.05.tar.bz2/src/rtl_eeprom.c -> r8168-8.048.00.tar.bz2/src/rtl_eeprom.c Changed
258
 
1
@@ -52,18 +52,17 @@
2
 //-------------------------------------------------------------------
3
 void rtl8168_eeprom_type(struct rtl8168_private *tp)
4
 {
5
-        void __iomem *ioaddr=tp->mmio_addr;
6
         u16 magic = 0;
7
 
8
         if (tp->mcfg == CFG_METHOD_DEFAULT)
9
                 goto out_no_eeprom;
10
 
11
-        if(RTL_R8(0xD2)&0x04) {
12
+        if(RTL_R8(tp, 0xD2)&0x04) {
13
                 //not support
14
                 //tp->eeprom_type = EEPROM_TWSI;
15
                 //tp->eeprom_len = 256;
16
                 goto out_no_eeprom;
17
-        } else if(RTL_R32(RxConfig) & RxCfg_9356SEL) {
18
+        } else if(RTL_R32(tp, RxConfig) & RxCfg_9356SEL) {
19
                 tp->eeprom_type = EEPROM_TYPE_93C56;
20
                 tp->eeprom_len = 256;
21
         } else {
22
@@ -80,28 +79,28 @@
23
         }
24
 }
25
 
26
-void rtl8168_eeprom_cleanup(void __iomem *ioaddr)
27
+void rtl8168_eeprom_cleanup(struct rtl8168_private *tp)
28
 {
29
         u8 x;
30
 
31
-        x = RTL_R8(Cfg9346);
32
+        x = RTL_R8(tp, Cfg9346);
33
         x &= ~(Cfg9346_EEDI | Cfg9346_EECS);
34
 
35
-        RTL_W8(Cfg9346, x);
36
+        RTL_W8(tp, Cfg9346, x);
37
 
38
-        rtl8168_raise_clock(&x, ioaddr);
39
-        rtl8168_lower_clock(&x, ioaddr);
40
+        rtl8168_raise_clock(tp, &x);
41
+        rtl8168_lower_clock(tp, &x);
42
 }
43
 
44
-int rtl8168_eeprom_cmd_done(void __iomem *ioaddr)
45
+int rtl8168_eeprom_cmd_done(struct rtl8168_private *tp)
46
 {
47
         u8 x;
48
         int i;
49
 
50
-        rtl8168_stand_by(ioaddr);
51
+        rtl8168_stand_by(tp);
52
 
53
         for (i = 0; i < 50000; i++) {
54
-                x = RTL_R8(Cfg9346);
55
+                x = RTL_R8(tp, Cfg9346);
56
 
57
                 if (x & Cfg9346_EEDO) {
58
                         udelay(RTL_CLOCK_RATE * 2 * 3);
59
@@ -119,7 +118,6 @@
60
 //-------------------------------------------------------------------
61
 u16 rtl8168_eeprom_read_sc(struct rtl8168_private *tp, u16 reg)
62
 {
63
-        void __iomem *ioaddr=tp->mmio_addr;
64
         int addr_sz = 6;
65
         u8 x;
66
         u16 data;
67
@@ -134,16 +132,16 @@
68
                 addr_sz = 8;
69
 
70
         x = Cfg9346_EEM1 | Cfg9346_EECS;
71
-        RTL_W8(Cfg9346, x);
72
+        RTL_W8(tp, Cfg9346, x);
73
 
74
-        rtl8168_shift_out_bits(RTL_EEPROM_READ_OPCODE, 3, ioaddr);
75
-        rtl8168_shift_out_bits(reg, addr_sz, ioaddr);
76
+        rtl8168_shift_out_bits(tp, RTL_EEPROM_READ_OPCODE, 3);
77
+        rtl8168_shift_out_bits(tp, reg, addr_sz);
78
 
79
-        data = rtl8168_shift_in_bits(ioaddr);
80
+        data = rtl8168_shift_in_bits(tp);
81
 
82
-        rtl8168_eeprom_cleanup(ioaddr);
83
+        rtl8168_eeprom_cleanup(tp);
84
 
85
-        RTL_W8(Cfg9346, 0);
86
+        RTL_W8(tp, Cfg9346, 0);
87
 
88
         return data;
89
 }
90
@@ -154,7 +152,6 @@
91
 //-------------------------------------------------------------------
92
 void rtl8168_eeprom_write_sc(struct rtl8168_private *tp, u16 reg, u16 data)
93
 {
94
-        void __iomem *ioaddr=tp->mmio_addr;
95
         u8 x;
96
         int addr_sz = 6;
97
         int w_dummy_addr = 4;
98
@@ -172,56 +169,56 @@
99
         }
100
 
101
         x = Cfg9346_EEM1 | Cfg9346_EECS;
102
-        RTL_W8(Cfg9346, x);
103
+        RTL_W8(tp, Cfg9346, x);
104
 
105
-        rtl8168_shift_out_bits(RTL_EEPROM_EWEN_OPCODE, 5, ioaddr);
106
-        rtl8168_shift_out_bits(reg, w_dummy_addr, ioaddr);
107
-        rtl8168_stand_by(ioaddr);
108
+        rtl8168_shift_out_bits(tp, RTL_EEPROM_EWEN_OPCODE, 5);
109
+        rtl8168_shift_out_bits(tp, reg, w_dummy_addr);
110
+        rtl8168_stand_by(tp);
111
 
112
-        rtl8168_shift_out_bits(RTL_EEPROM_ERASE_OPCODE, 3, ioaddr);
113
-        rtl8168_shift_out_bits(reg, addr_sz, ioaddr);
114
-        if (rtl8168_eeprom_cmd_done(ioaddr) < 0) {
115
+        rtl8168_shift_out_bits(tp, RTL_EEPROM_ERASE_OPCODE, 3);
116
+        rtl8168_shift_out_bits(tp, reg, addr_sz);
117
+        if (rtl8168_eeprom_cmd_done(tp) < 0) {
118
                 return;
119
         }
120
-        rtl8168_stand_by(ioaddr);
121
+        rtl8168_stand_by(tp);
122
 
123
-        rtl8168_shift_out_bits(RTL_EEPROM_WRITE_OPCODE, 3, ioaddr);
124
-        rtl8168_shift_out_bits(reg, addr_sz, ioaddr);
125
-        rtl8168_shift_out_bits(data, 16, ioaddr);
126
-        if (rtl8168_eeprom_cmd_done(ioaddr) < 0) {
127
+        rtl8168_shift_out_bits(tp, RTL_EEPROM_WRITE_OPCODE, 3);
128
+        rtl8168_shift_out_bits(tp, reg, addr_sz);
129
+        rtl8168_shift_out_bits(tp, data, 16);
130
+        if (rtl8168_eeprom_cmd_done(tp) < 0) {
131
                 return;
132
         }
133
-        rtl8168_stand_by(ioaddr);
134
+        rtl8168_stand_by(tp);
135
 
136
-        rtl8168_shift_out_bits(RTL_EEPROM_EWDS_OPCODE, 5, ioaddr);
137
-        rtl8168_shift_out_bits(reg, w_dummy_addr, ioaddr);
138
+        rtl8168_shift_out_bits(tp, RTL_EEPROM_EWDS_OPCODE, 5);
139
+        rtl8168_shift_out_bits(tp, reg, w_dummy_addr);
140
 
141
-        rtl8168_eeprom_cleanup(ioaddr);
142
-        RTL_W8(Cfg9346, 0);
143
+        rtl8168_eeprom_cleanup(tp);
144
+        RTL_W8(tp, Cfg9346, 0);
145
 }
146
 
147
-void rtl8168_raise_clock(u8 *x, void __iomem *ioaddr)
148
+void rtl8168_raise_clock(struct rtl8168_private *tp, u8 *x)
149
 {
150
         *x = *x | Cfg9346_EESK;
151
-        RTL_W8(Cfg9346, *x);
152
+        RTL_W8(tp, Cfg9346, *x);
153
         udelay(RTL_CLOCK_RATE);
154
 }
155
 
156
-void rtl8168_lower_clock(u8 *x, void __iomem *ioaddr)
157
+void rtl8168_lower_clock(struct rtl8168_private *tp, u8 *x)
158
 {
159
 
160
         *x = *x & ~Cfg9346_EESK;
161
-        RTL_W8(Cfg9346, *x);
162
+        RTL_W8(tp, Cfg9346, *x);
163
         udelay(RTL_CLOCK_RATE);
164
 }
165
 
166
-void rtl8168_shift_out_bits(int data, int count, void __iomem *ioaddr)
167
+void rtl8168_shift_out_bits(struct rtl8168_private *tp, int data, int count)
168
 {
169
         u8 x;
170
         int  mask;
171
 
172
         mask = 0x01 << (count - 1);
173
-        x = RTL_R8(Cfg9346);
174
+        x = RTL_R8(tp, Cfg9346);
175
         x &= ~(Cfg9346_EEDI | Cfg9346_EEDO);
176
 
177
         do {
178
@@ -230,62 +227,62 @@
179
                 else
180
                         x &= ~Cfg9346_EEDI;
181
 
182
-                RTL_W8(Cfg9346, x);
183
+                RTL_W8(tp, Cfg9346, x);
184
                 udelay(RTL_CLOCK_RATE);
185
-                rtl8168_raise_clock(&x, ioaddr);
186
-                rtl8168_lower_clock(&x, ioaddr);
187
+                rtl8168_raise_clock(tp, &x);
188
+                rtl8168_lower_clock(tp, &x);
189
                 mask = mask >> 1;
190
         } while(mask);
191
 
192
         x &= ~Cfg9346_EEDI;
193
-        RTL_W8(Cfg9346, x);
194
+        RTL_W8(tp, Cfg9346, x);
195
 }
196
 
197
-u16 rtl8168_shift_in_bits(void __iomem *ioaddr)
198
+u16 rtl8168_shift_in_bits(struct rtl8168_private *tp)
199
 {
200
         u8 x;
201
         u16 d, i;
202
 
203
-        x = RTL_R8(Cfg9346);
204
+        x = RTL_R8(tp, Cfg9346);
205
         x &= ~(Cfg9346_EEDI | Cfg9346_EEDO);
206
 
207
         d = 0;
208
 
209
         for (i = 0; i < 16; i++) {
210
                 d = d << 1;
211
-                rtl8168_raise_clock(&x, ioaddr);
212
+                rtl8168_raise_clock(tp, &x);
213
 
214
-                x = RTL_R8(Cfg9346);
215
+                x = RTL_R8(tp, Cfg9346);
216
                 x &= ~Cfg9346_EEDI;
217
 
218
                 if (x & Cfg9346_EEDO)
219
                         d |= 1;
220
 
221
-                rtl8168_lower_clock(&x, ioaddr);
222
+                rtl8168_lower_clock(tp, &x);
223
         }
224
 
225
         return d;
226
 }
227
 
228
-void rtl8168_stand_by(void __iomem *ioaddr)
229
+void rtl8168_stand_by(struct rtl8168_private *tp)
230
 {
231
         u8 x;
232
 
233
-        x = RTL_R8(Cfg9346);
234
+        x = RTL_R8(tp, Cfg9346);
235
         x &= ~(Cfg9346_EECS | Cfg9346_EESK);
236
-        RTL_W8(Cfg9346, x);
237
+        RTL_W8(tp, Cfg9346, x);
238
         udelay(RTL_CLOCK_RATE);
239
 
240
         x |= Cfg9346_EECS;
241
-        RTL_W8(Cfg9346, x);
242
+        RTL_W8(tp, Cfg9346, x);
243
 }
244
 
245
-void rtl8168_set_eeprom_sel_low(void __iomem *ioaddr)
246
+void rtl8168_set_eeprom_sel_low(struct rtl8168_private *tp)
247
 {
248
-        RTL_W8(Cfg9346, Cfg9346_EEM1);
249
-        RTL_W8(Cfg9346, Cfg9346_EEM1 | Cfg9346_EESK);
250
+        RTL_W8(tp, Cfg9346, Cfg9346_EEM1);
251
+        RTL_W8(tp, Cfg9346, Cfg9346_EEM1 | Cfg9346_EESK);
252
 
253
         udelay(20);
254
 
255
-        RTL_W8(Cfg9346, Cfg9346_EEM1);
256
+        RTL_W8(tp, Cfg9346, Cfg9346_EEM1);
257
 }
258
r8168-8.047.05.tar.bz2/src/rtl_eeprom.h -> r8168-8.048.00.tar.bz2/src/rtl_eeprom.h Changed
24
 
1
@@ -41,15 +41,15 @@
2
 #define RTL_CLOCK_RATE  3
3
 
4
 void rtl8168_eeprom_type(struct rtl8168_private *tp);
5
-void rtl8168_eeprom_cleanup(void __iomem *ioaddr);
6
+void rtl8168_eeprom_cleanup(struct rtl8168_private *tp);
7
 u16 rtl8168_eeprom_read_sc(struct rtl8168_private *tp, u16 reg);
8
 void rtl8168_eeprom_write_sc(struct rtl8168_private *tp, u16 reg, u16 data);
9
-void rtl8168_shift_out_bits(int data, int count, void __iomem *ioaddr);
10
-u16 rtl8168_shift_in_bits(void __iomem *ioaddr);
11
-void rtl8168_raise_clock(u8 *x, void __iomem *ioaddr);
12
-void rtl8168_lower_clock(u8 *x, void __iomem *ioaddr);
13
-void rtl8168_stand_by(void __iomem *ioaddr);
14
-void rtl8168_set_eeprom_sel_low(void __iomem *ioaddr);
15
+void rtl8168_shift_out_bits(struct rtl8168_private *tp, int data, int count);
16
+u16 rtl8168_shift_in_bits(struct rtl8168_private *tp);
17
+void rtl8168_raise_clock(struct rtl8168_private *tp, u8 *x);
18
+void rtl8168_lower_clock(struct rtl8168_private *tp, u8 *x);
19
+void rtl8168_stand_by(struct rtl8168_private *tp);
20
+void rtl8168_set_eeprom_sel_low(struct rtl8168_private *tp);
21
 
22
 
23
 
24
r8168-8.047.05.tar.bz2/src/rtltool.c -> r8168-8.048.00.tar.bz2/src/rtltool.c Changed
37
 
1
@@ -121,7 +121,7 @@
2
                         return -EPERM;
3
 
4
                 spin_lock_irqsave(&tp->lock, flags);
5
-                my_cmd.data = rtl8168_ephy_read(tp->mmio_addr, my_cmd.offset);
6
+                my_cmd.data = rtl8168_ephy_read(tp, my_cmd.offset);
7
                 spin_unlock_irqrestore(&tp->lock, flags);
8
 
9
                 if (copy_to_user(ifr->ifr_data, &my_cmd, sizeof(my_cmd))) {
10
@@ -136,7 +136,7 @@
11
                         return -EPERM;
12
 
13
                 spin_lock_irqsave(&tp->lock, flags);
14
-                rtl8168_ephy_write(tp->mmio_addr, my_cmd.offset, my_cmd.data);
15
+                rtl8168_ephy_write(tp, my_cmd.offset, my_cmd.data);
16
                 spin_unlock_irqrestore(&tp->lock, flags);
17
                 break;
18
 
19
@@ -144,7 +144,7 @@
20
                 my_cmd.data = 0;
21
                 if (my_cmd.len==1 || my_cmd.len==2 || my_cmd.len==4) {
22
                         spin_lock_irqsave(&tp->lock, flags);
23
-                        my_cmd.data = rtl8168_eri_read(tp->mmio_addr, my_cmd.offset, my_cmd.len, ERIAR_ExGMAC);
24
+                        my_cmd.data = rtl8168_eri_read(tp, my_cmd.offset, my_cmd.len, ERIAR_ExGMAC);
25
                         spin_unlock_irqrestore(&tp->lock, flags);
26
                 } else {
27
                         ret = -EOPNOTSUPP;
28
@@ -167,7 +167,7 @@
29
 
30
                 if (my_cmd.len==1 || my_cmd.len==2 || my_cmd.len==4) {
31
                         spin_lock_irqsave(&tp->lock, flags);
32
-                        rtl8168_eri_write(tp->mmio_addr, my_cmd.offset, my_cmd.len, my_cmd.data, ERIAR_ExGMAC);
33
+                        rtl8168_eri_write(tp, my_cmd.offset, my_cmd.len, my_cmd.data, ERIAR_ExGMAC);
34
                         spin_unlock_irqrestore(&tp->lock, flags);
35
                 } else {
36
                         ret = -EOPNOTSUPP;
37
Refresh


Request History
bitstreamout's avatar

bitstreamout created request about 5 years ago

- Update to new version 8.048.00
- Modify patch r8168-kernel_version.patch as upstream now supports 5.4

- Modify patch r8168-kernel_version.patch to let it build with 5.4


Hillwood Yang's avatar

hillwood accepted request about 5 years ago